Datasheet > CY7C9538-BLI

CY7C9538-BLI

更新时间： 2024-01-11 20:53:16

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
46页	762K
描述
OC-48/STM-16 Framer with Reconfigurable VC-POSIC2GVC-R

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技术参数
数据手册

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CY7C9538-BLI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	,
针数：	504	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.92
JESD-30 代码：	S-PBGA-B504	JESD-609代码：	e0
端子数量：	504	封装主体材料：	PLASTIC/EPOXY
封装形状：	SQUARE	封装形式：	GRID ARRAY
峰值回流温度（摄氏度）：	225	认证状态：	Not Qualified
表面贴装：	YES	电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER
端子面层：	TIN LEAD	端子形式：	BALL
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
Base Number Matches：	1

CY7C9538-BLI 数据手册

CONFIDENTIAL

CY7C9538

The following drawing demonstrates one possible combi-

nation of classification with the help of the Programmable

Frame Tagging Engine.

Programmable Frame Tagging Engine

The Programmable Frame Tagging Engine provides preclas-

sification of the packets/frames at the wire rate. This helps in

utilizing the link layer device more efficiently.

The following functions can be achieved with the help of the

Programmable Frame Tagging Engine:

The Programmable Frame Tagging Engine enables the user

to perform preclassification of all the incoming packets into

one of the 16 possible categories. Since each channel can

have up to 16 different categories, and up to 16 virtual concat-

enated channels are possible, this engine supports up to 256

different categories. For classification, two-pass comparison

can be specified. For each comparison a field of up to six bytes

can be selected within the first 64 bytes of the packet and

compared with up to 16 programmed values. The comparison

is on a bit by bit basis and any bit comparison can be masked

with a user programmable mask register. A four-bit tag is

attached to the cell/packet, based on the match. Host CPU can

program these parameters through register programming.

Incoming packet analysis to parse packets/frames/cells at wire

speed.

User-programmable routing of control packets to CPU for

processing.

Incoming frames tagged based on bits (such as congestion) in

incoming packets.

User-programmable offset to locate Ethernet and other frames

within DOS and other proprietary MAN networking protocols

to allow MPLS processing.

System Memory at

Host System

Tagging enables sorting of packets by

Host System

Tag #0

Control Packets

Data

Tag #1

Data

POSIC2GVC-R

Packets

Data

Tag #2

Packets not

belonging to this

Node

SONET/SDH

Data

Tag #n

........

Data

TTL-expired and

other discard

Tag #13

Data

packets

Errored packets

(CRC and Parity)

Tag #14

Data

Node-sourced

packets to be

sinked

Tag #15

Data

Figure 4. Frame Tagging Engine Data Sorting Diagram

Document #: 38-02095 Rev. *B

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