CONFIDENTIAL
CY7C9538
protection switching with only one device being main and
connected to link layer. The standby POSIC2GVC-R device is
connected to the main POSIC2GVC-R device and it is
controlled by host CPU. POSIC2GVC-R provides APS byte
information to the host CPU. The host CPU is expected to take
a protection switching decision and provide necessary instruc-
tions to both POSIC2GVC-R devices.
SONET/SDH Bypass
POSIC2GVC-R supports the SONET/SDH framer/deframer
bypass mode. Host CPU can program such bypass. In this
mode, the data frames/packets, encapsulated by one of the
encapsulators, will be transmitted transparently through VC
and SONET/SDH blocks to the fiber side and vice versa.
In case of protection switching, in the transmit direction, the
main POSIC2GVC-R will perform all other operations as
programmed, except some of the line and section processing
of SONET/SDH framing. The main POSIC2GVC-R device will
then pass on the SPEs to the standby device through the APS
port. The standby device will then perform the rest of the line
and section processing and transport SONET/SDH frames
over standby fiber.
System Interface
The system interface is programmable. For application in an
ATM system, POSIC2GVC-R system interface can be
programmed to be PHY side interface as per UTOPIA level 3
specifications.
For variable length packets, POSIC2GVC-R system interface
can be programmed to be OIF-SPI level 3. ATM cells can also
be transferred over OIF-SPI level 3 bus.
Similarly, in case of protection switched mode, on the receive
side, the standby device will process some of the line and
section overhead and transfer the frames to main device
through the APS port. The main device will perform the rest of
the processing in the receive side.
System interface can be programmed in HBST mode. In this
case, a separate set of address pins are supported on the
system side. This mode supports high-speed burst access.
CPU Interface
RxS
RxS
POSIC2GVC-R can interface with 16-bit or 32-bit CPU. The
CPU interface can be pin configured to be compatible with
Motorola or Intel bus interface. The CPU interface provides
access to all registers of POSIC2GVC-R, collates all interrupt
generated by various blocks and also supports control packet
transfers.
RxM
PHY STANDBY
POSIC STANDBY
TxS
TxS
Line Interface
The line interface/fiber side interface is configurable as 8 bit,
16-bit or 32-bit depending on the clock frequency and data
rate. The options shown in Table 3 are available.
RxS
RxM
PHY MAIN
RxM
Table 3. Configuration Options
LINK LAYER
DEVICE
POSIC MAIN
TxS
Bus Width
8 bits
Clock Frequency
19.44 MHz
Line Rate
OC-3/STM-1
8 bits
77.76 MHz
OC-12/STM-4
OC-12/STM-4
OC-48/STM-16
OC-48/STM-16
TxM
TxM
16 bits
16 bits
32 bits
38.88 MHz
Working Channel
Protection
155.52 MHz
77.76 MHz
Figure 5. POSIC2GVC-R APS Implementation using
Two POSIC2GVC-R Devices
Clock Source
The transmit clock can be programmed to be one of the
following sources:
Single Framer APS Implementation
A main and slave PHY device can be interfaced directly to the
main and APS ports of a single POSIC2GVC-R device. In this
case, the main PHY is connected to the main line interface and
the standby PHY is connected to the APS port.
Received clock supplied by the PHY
External transmit clock source.
APS Port
In the POSIC2GVC-R transmit path, SONET/SDH data is
bridged across the main and APS ports (per linear 1+1 APS
requirements). When protection switching, POSIC2GVC-R
can be programmed to switch line inputs from the main receive
port to the APS receive port, or vice versa.
POSIC2GVC-R provides a 16-bit APS port for 1+1 protection.
The support of a main and standby PHY interface connectivity
allows several different APS implementation options using
POSIC2GVC-R.
This APS scheme provides solely optical/PHY link level
protection.
Multi-Framer APS Implementation
Two POSIC2GVC-R devices can be connected to two different
transceivers, optics and fibers. POSIC2GVC-R enables
Document #: 38-02095 Rev. *B
Page 8 of 46
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