PRELIMINARY
CONFIDENTIAL
CY7C9548
10-Gigabit Ethernet LAN PHY-POSIC10GLAN™
— Detects and processes pause control frames in the
receive direction
— Supports generation of pause control frames under
the request of receive FIFO or as initiated by the
system
— Supports DA/SA/VLAN address filtering
• System/link layer interface
Features
• Compliant with 802.3ae specifications[1]
— Full-duplex media-access controller (MAC) data
transmission and reception
— 64B/66B PCS
— Rate adaptation
— Contains RMON for link statistics
• 10 GE features
— Performs flow control protocol per IEEE
802.3ae/D5.0
— 312.5-MHz DDR, 16-bit bus compliant with OIF
SPI-4-02.0[2]
• LAN SERDES Interface
— 644.53-MHz, 16-bit, compliant with IEEE XSBI
specifications[1]
— 160-Kbyte receive FIFO and 48-Kbyte transmit FIFO
— Supports transmit and receive RMON statistics
• CPU interface
— 32-bit CPU interface (up to 66 MHz)
— Appends optional CRC code to the current frame
under system request in the transmit direction and
performs optional CRC check in the receive
direction
— Programmable data padding in support of the
64-byte minimum packet size in the transmit
direction and optional pad extraction in the receive
direction
— Supports both Intel- and Motorola-type
microprocessors
• Two loop-back paths for diagnostics: system-side RS
loop-back, and line-side loop-back
• Compliant with IEEE 1149.1 JTAG boundary scan logic
standard
• 0.18-µm CMOS, 624-ball CBGA package
• +1.8V for core, +3.3V for LVTTL/LVDS
— Inserts Inter-Packet Gaps (IPG) in the transmit
direction and extracts IPGs in the receive direction
— Detects for packet Abort sequence and aborts
packets upon system command or FIFO overflow
Applications
• Edge routers
• Metro POP Ethernet switches
• Multi-service provisioning platforms
• 10 GE test equipment
• SAN/NAS
— Checks for the minimum and maximum packet
length and marks packets exceeding the maximum
packet length—option for length-based discard
— The PCS block implements a self-synchronous
scrambler and descrambler function
MDIO
Interface
CY7C9548
MDIO
TDAT[15:0]
TDCLK
FIFO/
FLOW
CONTROL
TXDATA[15:0]
10GE
MAC
TCTL
PCS
RS
RS
TXCLK
TSTAT[1:0]
TXCLK_SRC
TSCLK
XSBI
RDAT[15:0]
RXDATA[15:0]
RDCLK
RXCLK
FIFO/
FLOW
CONTROL
10GE
MAC
RCTL
SIG_DET
PCS
RSTAT[1:0]
RSCLK
Register
RMON
JTAG
Access
CPU
Interface
JTAG Interface
Figure 1. POSIC10GLAN (CY7C9548) Block Diagram
Notes:
1. IEEE Draft 802.3ae/D5.0, “Media Access Control (MAC) Parameters, Physical Layer, and Management Parameters for 10 Gb/s Operation,” May 1, 2002.
2. Optical Internetworking Forum (OIF) Implementation Agreement OIF-SPI-4-02.0, “System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface
for Physical and Link Layer Devices.” www.oiforum.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-02029 Rev. **
Revised August 21, 2002
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