PRELIMINARY
CONFIDENTIAL
CY7C9548
PCS
RS
MAC
SPI4-2
RX_CLK
RX PLL
RX_CLK[1:0]
RX_CLK
RSCLK
Gear Box
RSTAT[1:0]
RX
Block Sync
Descrambler
Decode
RXC[7:0]
RXP[63:0]
64B/66B
Rx
FIFO
RX RS
RXGC[15:0]
RXGD[63:0]
[63:0]
RDCLK
RDAT[15:0]
RCTL
XGMAC
RXD[63:0]
BER Monitor
TSCLK
TX_CLK
TXGC[15:0]
TXGD[63:0]
TX160_CK
TSTAT[1:0]
Flow
TXP[63:0]
TX_CLK
TX
TX
Scrambler &
PrePend
SYNC
[63:0]
[63:0]
TXC[7:0]
TX RS
Gear Box
66B/64B
Control
XGMAC
FIFO
Encode
TDAT[15:0]
TCTL
TXD]63:0]
TX156_CLK
TX PLL
TDCLK
RMON
CPU I/F
JTAG
MII
CPU
JTAG I/F
I/F
Figure 6. SPI4-2.0 to PCS Block Diagram
removes the preamble, and examines the received frames for
the correct CRC code against the calculated CRC code.
Functional Description
SPI4-2.0 to 10 GE MAC Block
Transmit Interface
The receive XGMAC contains twelve programmable registers
that can be used for exact-match MAC frame filtering. Five
different matching modes are provided:
In the transmit direction the TDAT[15:0], with its associated
source-synchronous clock TDCLK and control signal TCTL,
input the system-side data traffic to the transmit FIFO. The
control signal is used to identify the in-band control words. The
transmit FIFO status signals TSTAT[1:0] and TSCLK inform
the link layer of the status of the transmit FIFO along with
associated error detection and framing. Flow control is
provided to ensure proper FIFO operation and help prevent
FIFO overflow or underflow conditions. In the event that the
system side can not keep up with the current data rate, the
transmit FIFO underrun signal is generated.
SA or DA or VLAN or (DA and VLAN) or (SA and VLAN).
Matched frames can be passed to the SPI4-2.0 bus or
discarded.
POSIC10G offers a multicast hash address filter. This allows
the user to filter multiple multicast addresses at the device
without needing a full 48-bit match for each address. This kind
of filtering can be critical for accepting multicast packets only
for protocols supported by a system, or for rejecting traffic
destined for multicast destination groups of which the station
is not a member.
The transmit FIFO output data bus is synchronous to the
transmit clock, 156.25 MHz, generated by the transmit PLL.
This internal data bus is 64-bit-wide with associated
start-/end-of-frame signals.
10GE MAC Interface to RS
Transmit Interface
The 10 GE MAC output transmits data synchronous with the
156.25-MHz transmit clock to the RS circuitry.
The XGMAC transmit block performs all the MAC functions in
accordance with IEEE 802.3ae standards. It prepends
preamble, Start Frame Delineation (SFD), and Frame Check
Sequence (FCS) to the received MAC frame. Padding is
added to the data field to ensure a minimum payload size limit.
Depending on the configuration of the CY7C9548 the CRC
code may be appended to the current frame.
Receive Interface
The 10 GE MAC block receives data from the RS block
through a 64 bit data bus synchronous with the 156.25-MHz
clock signal generated from the receive RS circuitry.
RS to PCS Interface
Receive Interface
In the receive direction the 10 GE MAC circuitry outputs
frames onto a 64-bit data bus synchronous with the
156.25-MHz clock to the receive FIFO. When the receive FIFO
reaches a fill mark condition, it will issue a pause signal to
request the transmit 10 GE MAC framer to transmit a pause
control frame.
Transmit Interface
The transmit PCS block performs the required functionality of
the PCS sublayer as specified by IEEE 802.3ae specifications.
It receives the TXD[63:0] input data synchronous with a
divide-by-two version of the TDCLK signal, scrambles the
frame and 64B/66B encodes the scrambled stream. The
TXD[63:0] input is defined either as a frame data or code
character depending on the value of TXC[7:0]. The
66B/64B-encoded data bus is written in the transmit FIFO (in
the gearbox of Figure 6) with a write clock of 156.25 MHz
derived from TDCLK, and read out at the rate of 161 MHz. The
In addition the FIFO status signals allow for transmission of the
training sequence to the sink device for dynamic deskewing of
data.
The 10 GE MAC receive circuitry performs all the functions as
described in IEEE 802.3ae. It performs packet delineation,
Document #: 38-02029 Rev. **
Page 4 of 35
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