PRELIMINARY
CONFIDENTIAL
CY7C9548
The CY7C9548 device processes the incoming/outgoing
Ethernet packets and performs framing detection/insertion,
generation and insertion of Preamble/SFD. Timing is
performed relative to the system reference input clock (master
mode clocking) or SPI4-2.0 transmit clock (slave mode
clocking). On the transmit side the MAC framer calculates and
inserts the IPGs and also generates and processes Pause
control frames as initiated by the receive FIFO overflow
condition or as requested by the system. CRC codes are
calculated and optionally appended to the outgoing frames.
On the receive side the MAC framer processes the incoming
Ethernet packets and performs framing detection, and also
validates the CRC code. The frame timing is referenced to the
receive input reference clock. Packets containing CRC errors
are dropped, and those exceeding the user-specified size limit
are marked for processing by a higher layer device. The
receive MAC also detects, validates and extracts pause
control frames.
eight control signals, and the associated clock in each
direction. The data path is organized into eight lanes. Each
lane carries one octet of data. Delimiters and interpacket idle
characters are encoded on the TXD and RXD (refer to
Figure 6) with the control indicated by the assertion of TXC
and RXC, respectively. The PCS block comprises the PCS
transmit/receive, block synchronization, scrambling/descram-
bling of data, BER monitoring, and the 64B/66B block
encoding/decoding functions. In the receive direction two sync
bits are removed from the 66-bit frame after block synchroni-
zation and error monitoring. The received data stream is then
descrambled and decoded back into the 64-bit data bus. In the
transmit direction the 64-bit data bus is scrambled and
prepended with two sync bits according to the PCS 64B/66B
encoding scheme.
LANPHY Operation
The CY7C9548 device can be configured as a 10 GE MAC
standalone device for applications where an interface to a
LANPHY device is desired (refer to Figure 5). The output of
the 64/66 PCS block is muxed out onto the XSBI interface bus.
Internal configurable registers are provided to control and
program the minimum IPG, maximum frame size, preamble
checking and error frames discarded. A wide range of Ethernet
statistics are provided and are accessible by the micropro-
cessor for performance monitoring.
A
four-bit encoder/decoder performs the necessary
conversion between the 64/66 PCS 64-bit bus and the 16-bit
XSBI bus.
The MII block provides for management and the PHY control
functions. The internal XGMII is composed of a 64-bit bus,
PCS
64B/66B
RS
(RX)
10GMAC
(RX)
FIFO
&
64/16
FIFO
&
FLOW
Converter
CONTROL
PCS
RS
10GMAC
66B/64B
(TX)
(TX)
Figure 5. CY7C9548 LANPHY Operation
Document #: 38-02029 Rev. **
Page 3 of 35
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