Datasheet > CY7C9537-BLC

CY7C9537-BLC

更新时间： 2024-01-07 05:03:57

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
1页	33K
描述
Telecom IC,

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技术参数
数据手册

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CY7C9537-BLC 技术参数

生命周期：	Active	包装说明：	,
Reach Compliance Code：	compliant	风险等级：	5.7
Base Number Matches：	1

CY7C9537-BLC 数据手册

PRELIMINARY CONFIDENTIAL

CY7C9537

OC-48/STM-16 Framer - POSIC2G™

• ProgrammableA1A2processingbypassinRxdirection

with frame sync input

Features

• OC-48/STS-48/STM-16, OC-12/STS-12/STM-4,

OC-3/STS3/STM-1 rates, concatenated and

nonconcatenated

• Complete section overhead (SOH), line overhead

(LOH), and path overhead (POH) processing

• APS extraction, CPU interrupt generation, and

programmable insertion of APS byte

— Complies with ITU-Standards G.707/Y.1322 and

G.783

• Line side APS port interface

— Complies with Bellcore GR253 rev.1, 1997

• Provision for protection switching on SONET/ SDH port

• Programmable PRBS generator and receiver

• Serial port to access line/section data communication

channel (DCC) and voice communication channel

(VCC)

• FullduplexUTOPIA/OIF-SPI(POS-PHY)level3interface

• 16-bit/32-bit host CPU interface bus (Motorola/Intel

class)

— Channelized operation: supports 16xOC-3/STM-1

and 4xOC-12/STM-4 within OC48 stream

— Supports TUG3 mapping in SDH mode

• Full duplex mapping of ATM cells over SONET/SDH

— Complies with ITU-Standards I 432.2

• Full duplex mapping of packet-over-SONET/SDH: IETF

RFC 1619/1662/2615 (HDLC/PPP)

• JTAG and boundary scan

• Generic Protocol Encapsulator/Decapsulator delin-

eates packets/frames with length-CRC frame construct

• Glueless interface with Cypress CYS25G0101DX

OC-48 PHY

— Generic Framing Procedure (GFP) per ANSI T1X1.5

• User-programmable encapsulation

• User-programmable clear channel transport

• User-programmable SONET/SDH bypass

• Programmable frame tagging engine for packet pre-

classification enables features such as

• 0.18-µm CMOS, 504-pin BGA package

• +1.8V for core, +3.3V for LVTTL I/O, +1.5V/+3.3V for

HSTL/LVPECL I/O supply and +0.75V/2.0V reference

Applications

• Multi-service nodes

• ATM switches and routers

• Packet routers

• Multi-service routers

• SONET/SDH/add-drop mux for packet/data applica-

tions

— MPLS label lookup and tagging

— PPP: LCP and NCP tagging

— PPP control packets optionally sent to host CPU

interface

— MAC/layer 3 address lookup and tagging

• SONET/SDH/ATM/POS test equipment

E /O

W AN

D ata Link

C Y7C 9537

C YS 25G 0101D X

U TO P IA

O IF-S P I

H B S T

D evice

LAN and

C B R

O C -48

Transceiver

P O S IC 2G

ATM S AR

O /E

C P U

Figure 1. POSIC2G™ System Application Diagram

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-02063 Rev. **

Revised September 11, 2002

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