Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> CY7C9536B-BLC

CY7C9536B-BLC

更新时间： 2024-11-30 04:38:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		ATM集成电路 SONET集成电路 SDH集成电路电信集成电路电信电路异步传输模式
页数	文件大小	规格书
46页	761K
描述
OC-48/STM-16 Framer with VC - POSIC2GVC⑩

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CY7C9536B-BLC 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	LBGA,	针数：	50
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.81	Is Samacsys：	N
应用程序：	ATM;SDH;SONET	JESD-30 代码：	S-XBGA-B50
长度：	37.5 mm	功能数量：	1
端子数量：	50	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	UNSPECIFIED
封装代码：	LBGA	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	认证状态：	Not Qualified
座面最大高度：	1.57 mm	标称供电电压：	1.8 V
表面贴装：	YES	技术：	CMOS
电信集成电路类型：	ATM/SONET/SDH TRANSCEIVER	温度等级：	COMMERCIAL
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	宽度：	37.5 mm
Base Number Matches：	1

CY7C9536B-BLC 数据手册

CONFIDENTIAL

CY7C9536B

OC-48/STM-16 Framer with VC - POSIC2GVC™

• PPP control packets optionally sent to host CPU

interface

Features

• OC-48/STS-48/STM-16, OC-12/STS-12/STM-4,

OC-3/STS3/STM-1rates, concatenatedandnon-concat-

enated

• MAC/layer 3 address look up and tagging.

• ProgrammableA1A2processingbypassinRxdirection

with frame sync input

• Complies with ITU-Standards G.707/Y.1322 and

G.783^[1,2]

• Complies with Bellcore GR253 rev.1, 1997^[3]

• Complete section overhead (SOH), line overhead

(LOH), and path overhead (POH) processing

• APS extraction, CPU interrupt generation, and

programmable insertion of APS byte

• Channelizedoperation:supports16xOC-3and4xOC-12

within OC-48 stream

• Line side APS port interface

• Supports TUG3 mapping in SDH mode

• Provision for protection switching on SONET/SDH port

• Programmable PRBS generator and receiver

• Virtual concatenation enables secure and dedicated

bandwidth provisioning^[4]

• Serial port to access line/section data communication

channel (DCC) and voice communication channel

(VCC)

• Up to 16 channels

• From 50-Mbps to 1.2-Gbps bandwidth per channel

• STS-1 and STS-3c granularity

• Full duplex OIF-SPI (POS-PHY)/UTOPIA level 3

interface^[14,15]

• Full duplex mapping of ATM cells over SONET/SDH

• Complies with ITU-Standards I 432.2^[5,6,7]

• 16-bit/32-bit host CPU interface bus

• JTAG and boundary scan

• Full duplex mapping of packet-over-SONET/SDH: IETF

RFC 1619/1662/2615 (HDLC/PPP)^[8,9,10]

• Glueless interface with Cypress CYS25G0101DX

OC-48 PHY

• Generic Framing Procedure (GFP) per ANSI

T1X1.5^[11,12,13]Protocol Encapsulator/Decapsulator

delineates GFP frames with length-CRC frame

construct

• 0.18-um CMOS, 504-pin BGA package

• +1.8V for core, +3.3V for LVTTL I/O, +1.5V/+3.3V for

HSTL/LVPECL I/O supply, and +0.75V/2.0V reference

• GFP 268r1

Applications

• User-programmable encapsulation

• User-programmable clear channel transport

• User-programmable SONET/SDH bypass

• Multi-service nodes

• ATM switches and routers

• Programmable frame tagging engine for packet

preclassification enables such features as

• Packet routers and multiservice routers

• SONET/SDH/Add-Drop Mux for packet/data applications

• SONET/SDH/ATM/POS test equipment

• MPLS label lookup and tagging

• PPP: LCP and NCP tagging

Notes:

1. ITU-T Recommendation G.707. “Network Node Interface for the Synchronous Digital Hierarchy.” 1996.

2. ITU-T Recommendation G.783. “Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks.” 2000.

3. Bellcore Publication GR-253-Core. “Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria.” 1997.

4. Jones, N., Lucent Microelectronics, and C. Murton, Nortel Networks. “Extending PPP over SONET/DSH with Virtual Concatenation, High-Order and Low-Order

payloads.” Internet Draft. June 2000.

5. ITU-T Recommendation I.432.3. “B-ISDN User-Network Interface—Physical Layer Specification: 1544 kbit/s and 2048 kbit/s Operation.” 1999.

6. American National Standards Institute. “Synchronous Optical Network (SONET)—Basic Description Including Multiplex Structure, Rates and Formats.” ANSI

T1.105-1995.

7. American National Standards Institute. “Synchronous Optical Network (SONET)—Payload Mappings.” ANSI T1.105.02–1998.

8. Simpson, W. “PPP over SONET/SDH.” RFC 1619. May 1994.

9. Simpson, W., ed. “PPP in HDLC-like Framing,” RFC 1662. Daydreamer. July 1994.

10. Malis, A. and W. Simpson. “PPP over SONET/SDH,” RFC 2615. June 1999.

11. Hernandez-Valencia, E., Lucent Technologies. “A Generic Frame Format for Data over SONET (DoS).” March 2000.

12. Gorshe, C. and Steven. T1X1.5/99-204, T1 105.02. Draft Text for Mapping IEEE 802.3 Ethernet MAC Frames to SONET Payload. July 1999.

13. Hernandez-Valencia, E., Lucent Technologies. T1X1.5/2000-209. “Generic Framing Procedure (GFP) Specification.” October 9–13, 2000.

14. ATM Forum, Technical Committee. UUTOPIA 3 Physical Layer Interface.” Af-phy-0136.000. November 1999.

15. Can, R. and R. Tuck. “System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link-Layer Devices.” OIF-SPI3-01.0. June 2000.

Cypress Semiconductor Corporation

Document #: 38-02078 Rev. *G

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised April 25, 2005

12 3 4 5 6 7...46

中文翻译

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与CY7C9536B-BLC相关器件

型号	品牌	获取价格	描述	数据表
CY7C9536B-BLI	CYPRESS	获取价格	OC-48/STM-16 Framer with VC - POSIC2GVC⑩
CY7C9537B	CYPRESS	获取价格	OC-48/STM-16 Framer-POSIC2G
CY7C9537B-BLC	CYPRESS	获取价格	OC-48/STM-16 Framer-POSIC2G
CY7C9537B-BLI	CYPRESS	获取价格	OC-48/STM-16 Framer-POSIC2G
CY7C9537-BLC	CYPRESS	获取价格	Telecom IC,
CY7C9538	CYPRESS	获取价格	OC-48/STM-16 Framer with Reconfigurable VC-POSIC2GVC-R
CY7C9538-BLC	CYPRESS	获取价格	OC-48/STM-16 Framer with Reconfigurable VC-POSIC2GVC-R
CY7C9538-BLI	CYPRESS	获取价格	OC-48/STM-16 Framer with Reconfigurable VC-POSIC2GVC-R
CY7C9548-FAC	CYPRESS	获取价格	Telecom IC,
CY7C954ADX-AC	CYPRESS	获取价格	Transceiver, 1-Func, CMOS, PQFP100, PLASTIC, TQFP-100

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