Datasheet > CY7C1021D

CY7C1021D

更新时间： 2024-01-09 00:06:21

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	557K
描述
1-Mbit (64K x 16) Static RAM

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CY7C1021D 数据手册

CY7C1021D

1-Mbit (64K x 16) Static RAM

Features

Functional Description ^[1]

• Pin-and function-compatible with CY7C1021B

• High speed

The CY7C1021D is a high-performance CMOS static RAM

organized as 65,536 words by 16 bits. This device has an

automatic power-down feature that significantly reduces

power consumption when deselected. The input/output pins

(IO₀through IO₁₅) are placed in a high-impedance state when:

— t_AA= 10 ns

• Low active power

— I_CC= 80 mA @ 10 ns

• Deselected (CE HIGH)

• Outputs are disabled (OE HIGH)

• Low CMOS Standby Power

— I_SB2= 3 mA

• BHE and BLE are disabled (BHE, BLE HIGH)

• When the write operation is active (CE LOW, and WE LOW)

• 2.0V Data Retention

Write to the device by taking Chip Enable (CE) and Write

Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW,

then data from IO pins (IO₀through IO₇), is written into the

location specified on the address pins (A₀through A₁₅). If Byte

High Enable (BHE) is LOW, then data from IO pins (IO₈

through IO₁₅) is written into the location specified on the

address pins (A₀through A₁₅).

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Independent control of upper and lower bits

• Available in Pb-free 44-pin 400-Mil wide Molded SOJ and

44-pin TSOP II packages

Read from the device by taking Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH.

If Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appears on IO₀to IO₇.

If Byte High Enable (BHE) is LOW, then data from memory

appears on IO₈to IO₁₅. See the “Truth Table” on page 8 for a

complete description of read and write modes.

Logic Block Diagram

DATA IN DRIVERS

A₇

A₆

A₅

64K x 16

A₄

IO₀–IO₇

RAM Array

A₃

A₂

A₁

A₀

IO₈–IO₁₅

COLUMN DECODER

BHE

BLE

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05462 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 22, 2007

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与CY7C1021D相关器件

型号	品牌	获取价格	描述	数据表
CY7C1021D_11	CYPRESS	获取价格	1-Mbit (64 K × 16) Static RAM CMOS for Optimu
CY7C1021D-10VXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021D-10VXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1021D-10VXIT	CYPRESS	获取价格	1-Mbit (64 K Ã 16) Static RAM
CY7C1021D-10VXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1021D-10ZSXE	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021D-10ZSXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021D-10ZSXIT	CYPRESS	获取价格	Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1021DV33	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021DV33_10	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM

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