5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> CY7C1021DV33-12ZSXE
CY7C1021DV33-12ZSXE PDF预览

CY7C1021DV33-12ZSXE

更新时间： 2024-11-05 03:07:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
11页 382K
描述
1-Mbit (64K x 16) Static RAM

阅读下载

中文翻译

获取价格

CY7C1021DV33-12ZSXE 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSOP2
包装说明：TSOP2, TSOP44,.46,32针数：44
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.47
Is Samacsys：N最长访问时间：12 ns
I/O 类型：COMMONJESD-30 代码：R-PDSO-G44
JESD-609代码：e4长度：18.415 mm
内存密度：1048576 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：44
字数：65536 words字数代码：64000
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-40 °C组织：64KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装等效代码：TSOP44,.46,32
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
筛选级别：AEC-Q100座面最大高度：1.194 mm
最大待机电流：0.015 A最小待机电流：2 V
子类别：SRAMs最大压摆率：0.1 mA
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：10.16 mm
Base Number Matches：1

CY7C1021DV33-12ZSXE 数据手册

 浏览型号CY7C1021DV33-12ZSXE的Datasheet PDF文件第2页浏览型号CY7C1021DV33-12ZSXE的Datasheet PDF文件第3页浏览型号CY7C1021DV33-12ZSXE的Datasheet PDF文件第4页浏览型号CY7C1021DV33-12ZSXE的Datasheet PDF文件第5页浏览型号CY7C1021DV33-12ZSXE的Datasheet PDF文件第6页浏览型号CY7C1021DV33-12ZSXE的Datasheet PDF文件第7页 
CY7C1021DV33  
1-Mbit (64K x 16) Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
The CY7C1021DV33 is a high-performance CMOS static  
RAM organized as 65,536 words by 16 bits. This device has  
an automatic power-down feature that significantly reduces  
power consumption when deselected.  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• Pin-and function-compatible with CY7C1021CV33  
• High speed  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A15).  
— tAA = 10 ns  
• Low active power  
— ICC = 60 mA @ 10 ns  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the end of this data sheet for a complete  
description of Read and Write modes.  
• Low CMOS standby power  
— ISB2 = 3 mA  
• 2.0V data retention  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Independent control of upper and lower bits  
• Available in Pb-free 44-pin 400-Mil wide Molded SOJ,  
44-pin TSOP II and 48-ball VFBGA packages  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a Write operation  
(CE LOW, and WE LOW).  
The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil  
wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA  
packages.  
Logic Block Diagram  
DATA IN DRIVERS  
A7  
A6  
A5  
64K x 16  
A4  
I/O0–I/O7  
RAM Array  
A3  
A2  
A1  
A0  
I/O8–I/O15  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note  
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com  
Cypress Semiconductor Corporation  
Document #: 38-05460 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised November 8, 2006  
[+] Feedback  
1234567...11

中文翻译

下载PDF

CY7C1021DV33-12ZSXE 替代型号

型号 品牌 替代类型 描述 数据表
IDT71V016SA12PHI IDT

功能相似

 Standard SRAM, 64KX16, 12ns, CMOS, PDSO44

与CY7C1021DV33-12ZSXE相关器件

型号 品牌 获取价格 描述 数据表
CY7C1021DV33-8BAXC CYPRESS

获取价格

 		Standard SRAM, 64KX16, 8ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM, LEAD FREE, FBGA-48
CY7C1021DV33-8BAXI CYPRESS

获取价格

 		Standard SRAM, 64KX16, 8ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM, LEAD FREE, FBGA-48
CY7C1021DV33-8VXC CYPRESS

获取价格

 		Standard SRAM, 64KX16, 8ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44
CY7C1021DV33-8ZXC CYPRESS

获取价格

 		Standard SRAM, 64KX16, 8ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1021L-10ZC CYPRESS

获取价格

 		64K x 16 Static RAM
CY7C1021L-15ZC CYPRESS

获取价格

 		64K x 16 Static RAM
CY7C1021V30-15BAI ROCHESTER

获取价格

 		Standard SRAM, 128KX8, 15ns, CMOS, PBGA48, 7 X 7 MM, MINI, FBGA-48
CY7C1021V30L-15BSI CYPRESS

获取价格

 		Standard SRAM, 64KX16, 15ns, CMOS, PBGA48, 7.25 X 7.25 MM, MINI, BGA-48
CY7C1021V33L-10VC ETC

获取价格

 		x16 SRAM
CY7C1021V33L-12VCT CYPRESS

获取价格

 		Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44

与CY7C1021DV33-12ZSXE相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证