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CY7C1021V30-15BAI PDF预览

CY7C1021V30-15BAI

更新时间： 2023-12-18 00:00:00
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 静态存储器
页数 文件大小 规格书
7页 149K
描述
Standard SRAM, 128KX8, 15ns, CMOS, PBGA48, 7 X 7 MM, MINI, FBGA-48

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中文翻译

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CY7C1021V30-15BAI 技术参数

生命周期：Contact Manufacturer包装说明：BGA,
Reach Compliance Code：unknownECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.61
最长访问时间：15 nsJESD-30 代码：S-PBGA-B48
内存密度：1048576 bit内存集成电路类型：STANDARD SRAM
内存宽度：8功能数量：1
端子数量：48字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX8封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：SQUARE
封装形式：GRID ARRAY并行/串行：PARALLEL
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子位置：BOTTOM
Base Number Matches：1

CY7C1021V30-15BAI 数据手册

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0
CY7C1021V30  
64K x 16 Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
Features  
• 3.0V operation (2.7V–3.3V)  
• High speed  
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is  
1
8
written into the location specified on the address pins (A  
0
through A ). If Byte High Enable (BHE) is LOW, then data  
15  
— t = 15 ns  
AA  
from I/O pins (I/O through I/O ) is written into the location  
9
16  
• CMOS for optimum speed/power  
• Low active power (L version)  
specified on the address pins (A through A ).  
0
15  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
— 462 mW (max.)  
• Low CMOS Standby Power (L version)  
— 1.65 mW (max.)  
will appear on I/O to I/O . If Byte High Enable (BHE) is LOW,  
1
8
• Automatic power-down when deselected  
• Independent control of Upper and Lower bits  
• Available in a 48-ball Mini BGA package  
then data from memory will appear on I/O to I/O . See the  
9
16  
truth table at the back of this data sheet for a complete descrip-  
tion of read and write modes.  
The input/output pins (I/O through I/O ) are placed in a  
1
16  
Functional Description  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
The CY7C1021V30 is a high-performance CMOS static RAM  
organized as 65,536 words by 16 bits. This device has an au-  
tomatic power-down feature that significantly reduces power  
consumption when deselected.  
The CY7C1021V30 is available in a 48-ball Mini BGA package.  
Logic  
Diagram  
Block  
Pin Configuration  
DATA IN DRIVERS  
Mini BGA  
Top View  
1
2
3
4
6
5
A6  
A
B
A3 A7  
NC  
I/O  
BLE  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
OE  
A1  
A4  
A5  
NC  
A2  
A0  
CE  
I/O1 BHE  
I/O2 I/O3  
VSS I/O4  
16  
64K x 16  
I/O1–I/O8  
RAM Array  
512 X 2048  
I/O I/O  
C
14  
15  
I/O9–I/O16  
I/O  
NC  
NC  
VCC  
VSS  
D
E
13  
I/O  
I/O5  
I/O7  
NC  
VCC  
I/O6  
I/O8  
12  
I/O I/O  
A9 A8  
F
11  
10  
A10  
A14  
G
H
A11  
A13  
WE I/O9  
COLUMN DECODER  
A15  
NC  
NC A12  
BHE  
WE  
CE  
OE  
1021V30-2  
BLE  
1021V30-1  
2CY7C1021V30  
Selection Guide  
7C1021V30-15  
Maximum Access Time (ns)  
15  
190  
140  
5
Maximum Operating Current (mA)  
Industrial  
Industrial  
L
L
Maximum CMOS Standby Current (mA)  
[1]  
0.500  
Note:  
1. In addition: ISB2 < 300 µA at 2.7V.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
June 1, 1999  
1234567

中文翻译

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