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CY7C1021DV33-8BAXI

更新时间： 2024-11-05 14:35:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
11页 252K
描述
Standard SRAM, 64KX16, 8ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM, LEAD FREE, FBGA-48

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CY7C1021DV33-8BAXI 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：BGA
包装说明：TFBGA, BGA48,6X8,30针数：48
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.61
Is Samacsys：N最长访问时间：8 ns
I/O 类型：COMMONJESD-30 代码：S-PBGA-B48
JESD-609代码：e1长度：7 mm
内存密度：1048576 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：48
字数：65536 words字数代码：64000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：64KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装等效代码：BGA48,6X8,30
封装形状：SQUARE封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.003 A
最小待机电流：3 V子类别：SRAMs
最大压摆率：0.075 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：2.97 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：7 mmBase Number Matches：1

CY7C1021DV33-8BAXI 数据手册

 浏览型号CY7C1021DV33-8BAXI的Datasheet PDF文件第2页浏览型号CY7C1021DV33-8BAXI的Datasheet PDF文件第3页浏览型号CY7C1021DV33-8BAXI的Datasheet PDF文件第4页浏览型号CY7C1021DV33-8BAXI的Datasheet PDF文件第5页浏览型号CY7C1021DV33-8BAXI的Datasheet PDF文件第6页浏览型号CY7C1021DV33-8BAXI的Datasheet PDF文件第7页 
CY7C1021DV33  
PRELIMINARY  
1-Mbit (64K x 16) Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A15).  
Features  
• Pin- and function-compatible with CY7C1021CV33  
• High speed  
— tAA = 8 ns  
• CMOS for optimum speed/power  
• Low active power  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the end of this data sheet for a complete  
description of Read and Write modes.  
— ICC = 75 mA @ 8 ns  
• Low CMOS standby power  
— ISB2 = 3 mA  
• Data retention at 2.0V  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a Write operation  
(CE LOW, and WE LOW).  
• Available in 44-pin TSOP II, 400-mil SOJ, 48-ball FBGA  
Pb-Free Packages  
Functional Description[1]  
The CY7C1021DV33 is available in standard 44-pin TSOP  
Type II 400-mil-wide SOJ packages, as well as a 48-ball FBGA  
Pb-Free packages.  
The CY7C1021DV33 is a high-performance CMOS static  
RAM organized as 65,536 words by 16 bits. This device has  
an automatic power-down feature that significantly reduces  
power consumption when deselected.  
Logic Block Diagram  
Pin Configuration  
SOJ / TSOP II  
Top View  
DATA IN DRIVERS  
44  
43  
42  
41  
40  
39  
38  
1
2
3
4
5
6
A
A
5
4
A
A
3
6
A
A
7
OE  
2
A7  
A6  
A
1
BHE  
BLE  
I/O  
15  
I/O  
I/O  
A
0
CE  
A5  
A4  
A3  
A2  
A1  
64K x 16  
RAM Array  
512 X 2048  
I/O1–I/O8  
I/O  
7
0
37  
36  
35  
34  
33  
I/O  
I/O  
8
1
2
14  
13  
12  
I/O9–I/O16  
9
10  
11  
12  
13  
I/O  
V
SS  
I/O  
3
CC  
V
SS  
A0  
V
V
CC  
32  
31  
30  
29  
28  
27  
I/O  
I/O  
I/O  
4
5
6
7
11  
10  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
I/O  
9
8
COLUMN DECODER  
WE 17  
NC  
A
18  
19  
A
15  
8
BHE  
26  
25  
A
A
A
A
9
14  
13  
12  
WE  
CE  
OE  
20  
21  
22  
A
10  
A
11  
NC  
24  
23  
NC  
BLE  
Note:  
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05460 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised January 11, 2005  
1234567...11

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 		x16 SRAM
CY7C1021V33L-12VCT CYPRESS

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 		Standard SRAM, 64KX16, 12ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44
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 		Standard SRAM, 64KX16, 15ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44
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