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CY7C1022

更新时间： 2024-02-12 19:22:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
8页 126K
描述
32K x 16 Static RAM

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CY7C1022 数据手册

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022CY7C10  
PRELIMINARY  
CY7C1022  
32K x 16 Static RAM  
enable (BLE) is LOW, then data from I/O pins (I/O1 through  
I/O8), is written into the location specified on the address pins  
(A0 through A14). If byte high enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A14).  
Features  
• 5.0V operation (± 10%)  
• High speed  
— tAA = 12 ns  
Reading from the device is accomplished by taking chip en-  
able (CE) HIGH and output enable (OE) LOW while forcing the  
write enable (WE) HIGH. If byte low enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
will appear on I/O1 to I/O8. If byte high enable (BHE) is LOW,  
then data from memory will appear on I/O9 to I/O16. See the  
truth table at the back of this data sheet for a complete descrip-  
tion of read and write modes.  
• Low active power  
— 825 mW (max., 10 ns, “L” version)  
• Very Low standby power  
— 500 µW (max., “L” version)  
• Automatic power-down when deselected  
• Independent Control of Upper and Lower bytes  
• Available in 400-mil SOJ  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected (CE  
LOW), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
HIGH, and WE LOW).  
Functional Description  
The CY7C1022 is a high-performance CMOS static RAM or-  
ganized as 32,768 words by 16 bits. This device has an auto-  
matic power-down feature that significantly reduces power  
consumption when deselected.  
The CY7C1022 is available in standard 400-mil-wide SOJ  
packages.  
Writing to the device is accomplished by taking chip enable  
(CE) input HIGH and write enable (WE) input LOW. If byte low  
Logic Block Diagram  
Pin Configuration  
SOJ  
DATA IN DRIVERS  
Top View  
44  
NC  
1
A
0
43  
42  
41  
40  
39  
38  
A
A
14  
13  
12  
2
3
4
5
6
1
A
A
2
A
A
A
OE  
6
11  
A
BHE  
BLE  
I/O  
I/O  
I/O  
5
CE  
I/O  
I/O  
I/O  
A
A
A
4
3
2
1
32K x 16  
RAM Array  
I/O – I/O  
1
8
7
1
16  
37  
36  
35  
34  
33  
8
2
3
15  
14  
13  
I/O – I/O  
9
9
16  
A
A
10  
11  
12  
13  
I/O  
V
I/O  
4
0
V
SS  
CC  
V
V
SS  
CC  
32  
I/O  
I/O  
I/O  
5
6
7
8
12  
11  
31  
30  
29  
28  
I/O  
I/O  
I/O  
WE  
A
14  
15  
16  
17  
18  
19  
20  
21  
22  
I/O  
I/O  
10  
9
COLUMN DECODER  
NC  
27  
26  
25  
A
3
10  
9
BHE  
A
4
A
WE  
CE  
OE  
A
A
8
5
A
6
A
24  
23  
7
1022-2  
NC  
NC  
BLE  
2CY7C1022  
Selection Guide  
7C1022-12  
7C1022-15  
Maximum Access Time (ns)  
12  
170  
140  
3
15  
160  
130  
3
Maximum Operating Current (mA)  
L
L
Maximum CMOS Standby Current (mA)  
0.1  
0.1  
Shaded areas contain advance information.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05090 Rev. **  
Revised September 18, 2001  
12345678

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