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CY7C1024AV33-12BGI PDF预览

CY7C1024AV33-12BGI

更新时间: 2024-02-22 01:42:12
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 223K
描述
128K x 24 Static RAM

CY7C1024AV33-12BGI 数据手册

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024AV33  
CY7C1024AV33  
128K x 24 Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE1, CE2, CE3) active and Write Enable (WE) inputs LOW.  
Data on the 24 I/O pins (I/O0 through I/O23) is then written into  
the location specified on the address pins (A0 through A16).  
Features  
• High speed  
— tAA = 10 ns  
Reading from the device is accomplished by taking Chip  
Enable (CE1, CE2, CE3) active and Output Enable (OE) LOW  
while forcing Write Enable (WE) HIGH. Under these condi-  
tions, the contents of the memory location specified by the  
address pins will appear on the I/O pins.  
• CMOS for optimum speed/power  
• Center power/ground pinout  
• Automatic power-down when deselected  
• Easy memory expansion with CE1, CE2, CE3 and OE  
options  
The 24 input/output pins (I/O0 through I/O23) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE1, CE3 LOW, CE2 HIGH, and WE LOW).  
Functional Description[1]  
The CY7C1024AV33 is a high-performance CMOS static RAM  
organized as 131,072 words by 24 bits. Easy memory expan-  
sion is provided by an active LOW CE1, CE3, active HIGH  
CE2, an active LOW Output Enable (OE), and three-state driv-  
ers. This device has an automatic power-down feature that  
significantly reduces power consumption when deselected.  
The CY7C1024AV33 is available in a standard 119-ball BGA  
package and a 100-pin TQFP package.  
Functional Block Diagram  
VCC  
VSS  
A0  
DQ  
0
MEMORY ARRAY  
128K X 24  
DQ  
23  
CE#  
CE1#  
CE2  
WE#  
OE#  
COLUMN  
DECODER  
CONTROL  
A16  
Selection Guide  
7C1024AV33-10  
7C1024AV33-12  
7C1024AV33-15  
Maximum Access Time (ns)  
10  
275  
15  
12  
250  
15  
15  
225  
15  
Maximum Operating Current (mA)  
Maximum Standby Current (mA)  
Note:  
1. For guidelines on SRAM system design, please refer to the System Design GuidelinesCypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05149 Rev. *B  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised November 13, 2002  

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