Datasheet > CY7C1024DV33_09

CY7C1024DV33_09

更新时间： 2024-01-22 20:48:45

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	300K
描述
3-Mbit (128K X 24) Static RAM

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CY7C1024DV33_09 数据手册

CY7C1024DV33

3-Mbit (128K X 24) Static RAM

Features

Functional Description

■

High speed

t_AA= 10 ns

Low active power

I_CC= 175 mA at 10 ns

Low CMOS standby power

I_SB2= 25 mA

The CY7C1024DV33 is a high performance CMOS static RAM

organized as 128K words by 24 bits. This device has an

automatic power down feature that significantly reduces power

consumption when deselected.

❐

To write to the device, enable the chip (CE₁LOW, CE₂HIGH,

and CE₃LOW), while forcing the Write Enable (WE) input LOW.

❐

To read from the device, enable the chip by taking CE₁LOW, CE₂

HIGH, and CE₃LOW while forcing the Output Enable (OE) LOW

and the Write Enable (WE) HIGH. See the Truth Table on page

7 for a complete description of Read and Write modes.

■

Operating voltages of 3.3 ± 0.3V

2.0V data retention

The 24 I/O pins (I/O₀to I/O₂₃) are placed in a high impedance

state when the device is deselected (CE₁HIGH, CE₂LOW, or

CE₃HIGH) or when the output enable (OE) is HIGH during a

write operation. (CE₁LOW, CE₂HIGH, CE₃LOW, and WE

LOW).

Automatic power down when deselected

TTL compatible inputs and outputs

Easy memory expansion with CE₁, CE₂, and CE₃features

Available in Pb-free standard 119-ball PBGA

Logic Block Diagram

INPUT BUFFER

I/O₀– I/O₂₃

128K x 24

ARRAY

A_(9:0)

CE₁, CE₂, CE₃

COLUMN

DECODER

CONTROL LOGIC

A_(16:10)

Cypress Semiconductor Corporation

Document Number: 001-08353 Rev. *C

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised November 6, 2008

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