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CY7C1021DV33-10BAXI PDF预览

CY7C1021DV33-10BAXI

更新时间： 2024-09-25 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 564K
描述
Standard SRAM, 64KX16, 10ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM, LEAD FREE, FBGA-48

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CY7C1021DV33-10BAXI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：TFBGA, BGA48,6X8,30针数：48
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.09
最长访问时间：10 nsI/O 类型：COMMON
JESD-30 代码：S-PBGA-B48JESD-609代码：e1
长度：7 mm内存密度：1048576 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：48字数：65536 words
字数代码：64000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：64KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装等效代码：BGA48,6X8,30封装形状：SQUARE
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.003 A最小待机电流：3 V
子类别：SRAMs最大压摆率：0.06 mA
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：2.97 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：7 mm
Base Number Matches：1

CY7C1021DV33-10BAXI 数据手册

 浏览型号CY7C1021DV33-10BAXI的Datasheet PDF文件第2页浏览型号CY7C1021DV33-10BAXI的Datasheet PDF文件第3页浏览型号CY7C1021DV33-10BAXI的Datasheet PDF文件第4页浏览型号CY7C1021DV33-10BAXI的Datasheet PDF文件第5页浏览型号CY7C1021DV33-10BAXI的Datasheet PDF文件第6页浏览型号CY7C1021DV33-10BAXI的Datasheet PDF文件第7页 
CY7C1021DV33  
1-Mbit (64K x 16) Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
The CY7C1021DV33 is a high-performance CMOS static  
RAM organized as 65,536 words by 16 bits. This device has  
an automatic power-down feature that significantly reduces  
power consumption when deselected.  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• Pin-and function-compatible with CY7C1021CV33  
• High speed  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A15).  
— tAA = 10 ns  
• Low active power  
— ICC = 60 mA @ 10 ns  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the end of this data sheet for a complete  
description of Read and Write modes.  
• Low CMOS standby power  
— ISB2 = 3 mA  
• 2.0V data retention  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Independent control of upper and lower bits  
• Available in Pb-free 44-pin 400-Mil wide Molded SOJ,  
44-pin TSOP II and 48-ball VFBGA packages  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a Write operation  
(CE LOW, and WE LOW).  
The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil  
wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA  
packages.  
Logic Block Diagram  
DATA IN DRIVERS  
A7  
A6  
A5  
64K x 16  
A4  
I/O0–I/O7  
RAM Array  
A3  
A2  
A1  
A0  
I/O8–I/O15  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note  
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com  
Cypress Semiconductor Corporation  
Document #: 38-05460 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised December 14, 2010  
[+] Feedback  
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与CY7C1021DV33-10BAXI相关器件

型号 品牌 获取价格 描述 数据表
CY7C1021DV33-10BVXI CYPRESS

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 		1-Mbit (64K x 16) Static RAM
CY7C1021DV33-10BVXI INFINEON

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 		Asynchronous SRAM
CY7C1021DV33-10BVXIT CYPRESS

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 		Standard SRAM, 64KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 1MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1021DV33-10BVXIT INFINEON

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 		Asynchronous SRAM
CY7C1021DV33-10VXC CYPRESS

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 		暂无描述
CY7C1021DV33-10VXI CYPRESS

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 		1-Mbit (64K x 16) Static RAM
CY7C1021DV33-10VXI INFINEON

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 		Asynchronous SRAM
CY7C1021DV33-10VXIT CYPRESS

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 		Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, 0.400 INCH, ROHS COMPLIANT, SOJ-44
CY7C1021DV33-10VXIT INFINEON

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 		Asynchronous SRAM
CY7C1021DV33-10ZSXA CYPRESS

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 		1-Mbit (64K x 16) Static RAM

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