Datasheet > CY7C1021D-10VXIT

CY7C1021D-10VXIT

更新时间： 2024-11-06 14:56:15

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器
页数	文件大小	规格书
18页	1522K
描述
Asynchronous SRAM

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中文翻译

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数据手册

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CY7C1021D-10VXIT 数据手册

CY7C1021D

1-Mbit (64K × 16) Static RAM

1-Mbit (64K

× 16) Static RAM

automatic power down feature that significantly reduces power

consumption when deselected. The input and output pins (I/O₀

through I/O₁₅) are placed in a high impedance state when the

device is deselected (CE HIGH), outputs are disabled (OE

HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during

a write operation (CE LOW and WE LOW).

Features

■ Temperature Ranges:

❐ Industrial: –40 °C to 85 °C

❐ Automotive-A: –40 °C to 85 °C

■ Pin and Function Compatible with CY7C1021B

Write to the device by taking Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from I/O pins (I/O₀through I/O₇), is written into the location

specified on the address pins (A₀through A₁₅). If Byte High

Enable (BHE) is LOW, then data from I/O pins (I/O₈through

I/O₁₅) is written into the location specified on the address pins

(A₀through A₁₅).

■ High Speed

❐ t_AA= 10 ns

■ Low Active Power

❐ I_CC= 80 mA at 10 ns

■ Low CMOS Standby Power

❐ I_SB2= 3 mA

Read from the device by taking Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appears on I/O₀to I/O₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on I/O₈to I/O₁₅. See the Truth Table on page 10 for a

complete description of read and write modes.

■ 2.0 V Data Retention

■ Automatic Power Down when Deselected

■ CMOS for Optimum Speed and Power

■ Independent Control of Upper and Lower Bits

The CY7C1021D device is suitable for interfacing with

processors that have TTL I/P levels. It is not suitable for

processors that require CMOS I/P levels. Please see Electrical

Characteristics on page 4 for more details and suggested

alternatives.

■ Available in Pb-free 44-pin 400 Mils Wide Molded SOJ and

44-pin TSOP II Packages

Functional Description

For a complete list of related documentation, click here.

The CY7C1021D is a high performance CMOS static RAM

organized as 65,536 words by 16 bits. This device has an

Logic Block Diagram

DATA IN DRIVERS

A₇

A₆

A₅

64K x 16

A₄

I/O₀–I/O₇

RAM Array

A₃

A₂

A₁

A₀

I/O₈–I/O₁₅

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 38-05462 Rev. *O

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 2, 2016

12 3 4 5 6 7...18

中文翻译

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与CY7C1021D-10VXIT相关器件

型号	品牌	获取价格	描述	数据表
CY7C1021D-10ZSXE	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021D-10ZSXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021D-10ZSXIT	CYPRESS	获取价格	Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1021DV33	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021DV33_10	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021DV33-10BAXI	CYPRESS	获取价格	Standard SRAM, 64KX16, 10ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM, LEAD FREE, FBGA-48
CY7C1021DV33-10BVXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021DV33-10BVXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1021DV33-10BVXIT	CYPRESS	获取价格	Standard SRAM, 64KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 1MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1021DV33-10BVXIT	INFINEON	获取价格	Asynchronous SRAM

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