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CY7C1021DV33-10ZSXIT PDF预览

CY7C1021DV33-10ZSXIT

更新时间： 2024-11-19 12:56:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 360K
描述
1-Mbit (64 K x 16) Static RAM

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中文翻译

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CY7C1021DV33-10ZSXIT 数据手册

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CY7C1021DV33  
1-Mbit (64 K x 16) Static RAM  
Features  
Functional Description[1]  
■ Temperature ranges  
❐ Industrial: –40 °C to 85 °C  
❐ Automotive-A: –40 °C to 85 °C  
The CY7C1021DV33 is a high-performance CMOS static  
RAM organized as 65,536 words by 16 bits. This device has  
an automatic power-down feature that significantly reduces  
power consumption when deselected.  
■ Pin-and function-compatible with CY7C1021CV33  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A15).  
■ High speed  
❐ tAA = 10 ns  
■ Low active power  
❐ ICC = 60 mA @ 10 ns  
■ Low CMOS standby power  
❐ ISB2 = 3 mA  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the end of this data sheet for a complete  
description of Read and Write modes.  
■ 2.0 V data retention  
■ Automatic power-down when deselected  
■ CMOS for optimum speed/power  
■ Independent control of upper and lower bits  
■ Available in Pb-free 44-pin 400-Mil wide molded SOJ,  
44-pin TSOP II and 48-ball VFBGA packages  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a Write operation  
(CE LOW, and WE LOW).  
The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil  
wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA  
packages.  
Logic Block Diagram  
DATA IN DRIVERS  
A7  
A6  
A5  
64K x 16  
A4  
I/O0–I/O7  
RAM Array  
A3  
A2  
A1  
A0  
I/O8–I/O15  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Cypress Semiconductor Corporation  
Document #: 38-05460 Rev. *G  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised October 25, 2011  
1234567...13

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CY7C1021DV33-10ZSXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1021DV33-10ZSXA CYPRESS

完全替代

 1-Mbit (64K x 16) Static RAM
CY7C1021DV33-10ZSXI CYPRESS

类似代替

 1-Mbit (64K x 16) Static RAM
71V016SA15PHGI8 IDT

功能相似

 3.3V CMOS Static RAM

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CY7C1021V30L-15BSI CYPRESS

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