Datasheet > CY7C1021DV33_10

CY7C1021DV33_10

更新时间： 2024-11-19 09:43:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	564K
描述
1-Mbit (64K x 16) Static RAM

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CY7C1021DV33_10 数据手册

CY7C1021DV33

1-Mbit (64K x 16) Static RAM

Features

Functional Description^[1]

• Temperature Ranges

The CY7C1021DV33 is a high-performance CMOS static

RAM organized as 65,536 words by 16 bits. This device has

an automatic power-down feature that significantly reduces

power consumption when deselected.

— Industrial: –40°C to 85°C

— Automotive-A: –40°C to 85°C

— Automotive-E: –40°C to 125°C

• Pin-and function-compatible with CY7C1021CV33

• High speed

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀

through A₁₅). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₅).

— t_AA= 10 ns

• Low active power

— I_CC= 60 mA @ 10 ns

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀to I/O₇. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the truth table at the end of this data sheet for a complete

description of Read and Write modes.

• Low CMOS standby power

— I_SB2= 3 mA

• 2.0V data retention

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Independent control of upper and lower bits

• Available in Pb-free 44-pin 400-Mil wide Molded SOJ,

44-pin TSOP II and 48-ball VFBGA packages

The input/output pins (I/O₀through I/O₁₅) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a Write operation

(CE LOW, and WE LOW).

The CY7C1021DV33 is available in Pb-free 44-pin 400-Mil

wide Molded SOJ, 44-pin TSOP II and 48-ball VFBGA

packages.

Logic Block Diagram

DATA IN DRIVERS

A₇

A₆

A₅

64K x 16

A₄

I/O₀–I/O₇

RAM Array

A₃

A₂

A₁

A₀

I/O₈–I/O₁₅

COLUMN DECODER

BHE

BLE

Note

1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com

Cypress Semiconductor Corporation

Document #: 38-05460 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised December 14, 2010

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与CY7C1021DV33_10相关器件

型号	品牌	获取价格	描述	数据表
CY7C1021DV33-10BAXI	CYPRESS	获取价格	Standard SRAM, 64KX16, 10ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM, LEAD FREE, FBGA-48
CY7C1021DV33-10BVXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021DV33-10BVXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1021DV33-10BVXIT	CYPRESS	获取价格	Standard SRAM, 64KX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 1MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1021DV33-10BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1021DV33-10VXC	CYPRESS	获取价格	暂无描述
CY7C1021DV33-10VXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY7C1021DV33-10VXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1021DV33-10VXIT	CYPRESS	获取价格	Standard SRAM, 64KX16, 10ns, CMOS, PDSO44, 0.400 INCH, ROHS COMPLIANT, SOJ-44
CY7C1021DV33-10VXIT	INFINEON	获取价格	Asynchronous SRAM

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