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CY7C1020CV33-15ZE PDF预览

CY7C1020CV33-15ZE

更新时间： 2024-01-31 02:12:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
9页 263K
描述
512K (32K x 16) Static RAM

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CY7C1020CV33-15ZE 技术参数

生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP2,针数：44
Reach Compliance Code：unknownECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.32
最长访问时间：15 nsJESD-30 代码：R-PDSO-G44
JESD-609代码：e3/e4长度：18.415 mm
内存密度：524288 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：44字数：32768 words
字数代码：32000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：32KX16封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1.194 mm
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：2.97 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN/NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
宽度：10.16 mmBase Number Matches：1

CY7C1020CV33-15ZE 数据手册

 浏览型号CY7C1020CV33-15ZE的Datasheet PDF文件第2页浏览型号CY7C1020CV33-15ZE的Datasheet PDF文件第3页浏览型号CY7C1020CV33-15ZE的Datasheet PDF文件第4页浏览型号CY7C1020CV33-15ZE的Datasheet PDF文件第5页浏览型号CY7C1020CV33-15ZE的Datasheet PDF文件第6页浏览型号CY7C1020CV33-15ZE的Datasheet PDF文件第7页 
CY7C1020CV33  
512K (32K x 16) Static RAM  
Features  
Functional Description  
• Pin- and function-compatible with CY7C1020V33  
• Temperature Ranges  
The CY7C1020CV33 is a high-performance CMOS static  
RAM organized as 32,768 words by 16 bits. This device has  
an automatic power-down feature that significantly reduces  
power consumption when deselected.  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• High speed  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A14). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A14).  
— tAA = 10 ns  
• CMOS for optimum speed/power  
• Low active power  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O9 to I/O16. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
— 325 mW (max.)  
• Automatic power-down when deselected  
• Independent control of upper and lower bits  
• Available in Pb-free and non Pb-free 44-pin TSOP II  
package  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
The CY7C1020CV33 is available in standard 44-pin TSOP  
Type II package.  
PinConfiguration[1]  
Logic Block Diagram  
TSOP II  
Top View  
DATA IN DRIVERS  
44  
1
2
3
4
5
6
NC  
A
5
43  
42  
41  
40  
39  
38  
A
A
3
6
A
A
2
7
A7  
A6  
OE  
A
1
BHE  
BLE  
I/O  
A
0
A5  
A4  
A3  
A2  
A1  
A0  
32K × 16  
CE  
I/O1–I/O8  
RAM Array  
I/O  
7
1
16  
37  
36  
35  
34  
33  
I/O  
I/O  
8
I/O  
I/O  
2
3
15  
14  
13  
I/O9–I/O16  
9
10  
11  
12  
13  
I/O  
V
SS  
I/O  
4
CC  
V
SS  
V
V
CC  
32  
31  
30  
29  
28  
27  
I/O  
I/O  
I/O  
5
6
7
8
12  
11  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
10  
9
COLUMN DECODER  
I/O  
WE 17  
A4  
NC  
18  
A
8
BHE  
19  
26  
25  
A
13  
A
14  
9
WE  
CE  
OE  
A
20  
21  
22  
A
11  
10  
A
A
12  
24  
23  
NC  
NC  
BLE  
Note:  
1. NC pins are not connected on the die  
Cypress Semiconductor Corporation  
Document #: 38-05133 Rev. *E  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 3, 2006  
[+] Feedback  
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