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CY7C1020DV33-10ZSXIT PDF预览

CY7C1020DV33-10ZSXIT

更新时间： 2024-11-06 14:56:19
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器
页数 文件大小 规格书
13页 329K
描述
Asynchronous SRAM

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CY7C1020DV33-10ZSXIT 数据手册

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CY7C1020DV33  
512 K (32 K x 16) Static RAM  
Writing to the device is accomplished by taking chip enable  
(CE) and write enable (WE) inputs LOW. If byte low enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A14). If byte high enable (BHE) is LOW, then data from  
I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A14).  
Features  
■ Pin-and function-compatible with CY7C1020CV33  
■ High speed  
❐ tAA = 10 ns  
■ Low active power  
Reading from the device is accomplished by taking chip  
enable (CE) and output enable (OE) LOW while forcing the  
write enable (WE) HIGH. If byte low enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
will appear on I/O0 to I/O7. If byte high enable (BHE) is LOW,  
then data from memory will appear on I/O8 to I/O15. See the  
truth table at the back of this data sheet for a complete  
description of read and write modes.  
❐ ICC = 60 mA @ 10 ns  
■ Low CMOS standby power  
❐ ISB2 = 3 mA  
■ 2.0 V Data retention  
■ Automatic power-down when deselected  
■ CMOS for optimum speed/power  
■ Independent control of upper and lower bits  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
■ Available in Pb-free 44-pin 400-Mil wide Molded SOJ and  
44-pin TSOP II packages  
Functional Description  
The CY7C1020DV33 is available in Pb-free 44-pin 400-Mil  
wide Molded SOJ and 44-pin TSOP II packages.  
The CY7C1020DV33 is a high-performance CMOS static  
RAM organized as 32,768 words by 16 bits. This device has  
an automatic power-down feature that significantly reduces  
power consumption when deselected.  
For a complete list of related documentation, click here.  
Pin Configuration[1]  
SOJ/TSOP II  
Logic Block Diagram  
Top View  
DATA IN DRIVERS  
A
A
A
OE  
BHE  
BLE  
I/O  
15  
I/O  
I/O  
13  
I/O  
NC  
A
1
2
3
4
5
6
7
8
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
5
6
7
3
A
2
A7  
A6  
A5  
A
1
A
0
32K x 16  
A4  
CE  
I/O  
0
I/O0–I/O7  
RAM Array  
A3  
I/O  
A2  
A1  
A0  
I/O8–I/O15  
1
14  
I/O  
9
2
I/O  
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
3
12  
V
SS  
CC  
V
SS  
I/O  
V
CC  
I/O  
I/O  
I/O  
I/O  
4
11  
10  
I/O  
5
COLUMN DECODER  
I/O  
6
9
I/O  
7
8
BHE  
WE  
A
NC  
A
WE  
CE  
OE  
4
14  
8
A
A
9
A
13  
12  
A
A
10  
11  
A
BLE  
NC  
NC  
Notes  
1. NC pins are not connected on the die.  
Cypress Semiconductor Corporation  
Document Number: 38-05461 Rev. *I  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised November 19, 2014  
1234567...13

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