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CY7C1020D-10ZSXIT PDF预览

CY7C1020D-10ZSXIT

更新时间： 2023-09-03 20:29:23
品牌 Logo 应用领域
英飞凌 - INFINEON 时钟静态存储器光电二极管内存集成电路
页数 文件大小 规格书
17页 534K
描述
Asynchronous SRAM

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中文翻译

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CY7C1020D-10ZSXIT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：ActiveReach Compliance Code：compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.81最长访问时间：10 ns
最大时钟频率 (fCLK)：100 MHzI/O 类型：COMMON
JESD-30 代码：R-PDSO-G44JESD-609代码：e4
内存密度：524288 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
端子数量：44字数：32768 words
字数代码：32000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：32KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP
封装等效代码：TSOP44,.46,32封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
电源：5 V认证状态：Not Qualified
最大待机电流：0.003 A最小待机电流：2 V
子类别：SRAMs最大压摆率：0.08 mA
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL

CY7C1020D-10ZSXIT 数据手册

 浏览型号CY7C1020D-10ZSXIT的Datasheet PDF文件第2页浏览型号CY7C1020D-10ZSXIT的Datasheet PDF文件第3页浏览型号CY7C1020D-10ZSXIT的Datasheet PDF文件第4页浏览型号CY7C1020D-10ZSXIT的Datasheet PDF文件第5页浏览型号CY7C1020D-10ZSXIT的Datasheet PDF文件第6页浏览型号CY7C1020D-10ZSXIT的Datasheet PDF文件第7页 
CY7C1020D  
512-Kbit (32 K × 16) Static RAM  
512-Kbit (32  
K × 16) Static RAM  
■ Deselected (CE HIGH)  
Features  
■ Outputs are disabled (OE HIGH)  
■ Pin- and function-compatible with CY7C1020B  
■ BHE and BLE are disabled (BHE, BLE HIGH)  
■ When the write operation is active (CE LOW, and WE LOW)  
■ High speed  
❐ tAA = 10 ns  
Write to the device by taking Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from IO pins (IO0 through IO7), is written into the location  
specified on the address pins (A0 through A14). If Byte High  
■ Low active power  
❐ ICC = 80 mA @ 10 ns  
■ Low complementary metal oxide semiconductor (CMOS)  
standby power  
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15  
)
is written into the location specified on the address pins (A0  
through A14).  
❐ ISB2 = 3 mA  
■ 2.0 V data retention  
Reading from the device by taking Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appears on IO0 to IO7. If  
Byte High Enable (BHE) is LOW, then data from memory  
appears on IO8 to IO15. See the “Truth Table” on page 11 for a  
complete description of read and write modes.  
■ Automatic power-down when deselected  
■ CMOS for optimum speed/power  
■ Independent control of upper and lower bits  
■ Available in Pb-free 44-pin 400-Mil wide Molded SOJ and  
44-pin thin small outline package (TSOP) II packages  
The CY7C1020D device is suitable for interfacing with  
processors that have TTL I/P levels. It is not suitable for  
processors that require CMOS I/P levels. Please see Electrical  
Characteristics on page 4 for more details and suggested  
alternatives.  
Functional Description  
[1]  
The CY7C1020D  
is a high-performance CMOS static RAM  
organized as 32,768 words by 16 bits. This device has an  
automatic power-down feature that significantly reduces power  
consumption when deselected.The input and output pins  
(IO0 through IO15) are placed in a high-impedance state when:  
For a complete list of related documentation, click here.  
Logic Block Diagram  
DATA IN DRIVERS  
A
A
7
6
5
4
A
32K x 16  
A
A
A
A
A
IO –IO  
0
7
RAM Array  
3
2
1
0
IO –IO  
8
15  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document Number: 38-05463 Rev. *J  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised November 28, 2014  
1234567...17

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CY7C1020DV33-10VXI CYPRESS

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CY7C1020DV33-10VXIT CYPRESS

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CY7C1020DV33-10ZSXI INFINEON

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