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CY7C1020DV33_10

更新时间： 2024-02-16 22:05:41
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 527K
描述
512K (32K x 16) Static RAM

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CY7C1020DV33_10 数据手册

 浏览型号CY7C1020DV33_10的Datasheet PDF文件第2页浏览型号CY7C1020DV33_10的Datasheet PDF文件第3页浏览型号CY7C1020DV33_10的Datasheet PDF文件第4页浏览型号CY7C1020DV33_10的Datasheet PDF文件第5页浏览型号CY7C1020DV33_10的Datasheet PDF文件第6页浏览型号CY7C1020DV33_10的Datasheet PDF文件第7页 
CY7C1020DV33  
512K (32K x 16) Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A14). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A14).  
Features  
• Pin-and function-compatible with CY7C1020CV33  
• High speed  
— tAA = 10 ns  
• Low active power  
— ICC = 60 mA @ 10 ns  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Low CMOS standby power  
— ISB2 = 3 mA  
• 2.0V Data retention  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Independent control of upper and lower bits  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
• Available in Pb-free 44-pin 400-Mil wide Molded SOJ and  
44-pin TSOP II packages  
Functional Description[1]  
The CY7C1020DV33 is available in Pb-free 44-pin 400-Mil  
wide Molded SOJ and 44-pin TSOP II packages.  
The CY7C1020DV33 is a high-performance CMOS static  
RAM organized as 32,768 words by 16 bits. This device has  
an automatic power-down feature that significantly reduces  
power consumption when deselected.  
Logic Block Diagram  
Pin Configuration[2]  
SOJ/TSOP II  
Top View  
DATA IN DRIVERS  
A
A
A
OE  
BHE  
BLE  
NC  
A
1
2
3
4
5
6
7
8
44  
43  
42  
41  
40  
39  
38  
37  
5
6
7
3
A
2
A
1
A7  
A6  
A5  
A
0
CE  
I/O  
0
32K x 16  
A4  
I/O  
15  
I/O  
I/O0–I/O7  
RAM Array  
A3  
I/O  
1
14  
A2  
A1  
A0  
I/O  
I/O8–I/O15  
9
I/O  
13  
I/O  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
2
I/O  
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
3
12  
V
CC  
SS  
V
SS  
I/O  
V
CC  
I/O  
4
11  
10  
I/O  
I/O  
5
I/O  
I/O  
I/O  
6
9
COLUMN DECODER  
I/O  
7
8
WE  
A
NC  
A
BHE  
WE  
CE  
4
14  
8
A
A
9
A
A
A
13  
12  
10  
11  
OE  
A
BLE  
NC  
NC  
Notes  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com  
2. NC pins are not connected on the die.  
Cypress Semiconductor Corporation  
Document #: 38-05461 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised December 14, 2010  
[+] Feedback  
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