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CY7C1020DV33-12ZSXE PDF预览

CY7C1020DV33-12ZSXE

更新时间： 2024-01-15 00:17:32
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 330K
描述
512K (32K x 16) Static RAM

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CY7C1020DV33-12ZSXE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSOP2
包装说明：TSOP2, TSOP44,.46,32针数：44
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.82
最长访问时间：12 nsI/O 类型：COMMON
JESD-30 代码：R-PDSO-G44JESD-609代码：e4
长度：18.415 mm内存密度：524288 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：44字数：32768 words
字数代码：32000工作模式：ASYNCHRONOUS
最高工作温度：125 °C最低工作温度：-40 °C
组织：32KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装等效代码：TSOP44,.46,32封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified筛选级别：AEC-Q100
座面最大高度：1.194 mm最大待机电流：0.015 A
最小待机电流：2 V子类别：SRAMs
最大压摆率：0.1 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：10.16 mm

CY7C1020DV33-12ZSXE 数据手册

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CY7C1020DV33  
512K (32K x 16) Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A14). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A14).  
Features  
• Pin-and function-compatible with CY7C1020CV33  
• High speed  
— tAA = 10 ns  
• Low active power  
— ICC = 60 mA @ 10 ns  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Low CMOS standby power  
— ISB2 = 3 mA  
• 2.0V Data retention  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Independent control of upper and lower bits  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
• Available in Pb-free 44-pin 400-Mil wide Molded SOJ and  
44-pin TSOP II packages  
Functional Description[1]  
The CY7C1020DV33 is available in Pb-free 44-pin 400-Mil  
wide Molded SOJ and 44-pin TSOP II packages.  
The CY7C1020DV33 is a high-performance CMOS static  
RAM organized as 32,768 words by 16 bits. This device has  
an automatic power-down feature that significantly reduces  
power consumption when deselected.  
Logic Block Diagram  
Pin Configuration[2]  
SOJ/TSOP II  
Top View  
DATA IN DRIVERS  
A
A
A
OE  
BHE  
BLE  
NC  
A
1
2
3
4
5
6
7
8
44  
43  
42  
41  
40  
39  
38  
37  
5
6
7
3
A
2
A
1
A7  
A6  
A5  
A
0
CE  
I/O  
0
32K x 16  
A4  
I/O  
15  
I/O  
I/O0–I/O7  
RAM Array  
A3  
I/O  
1
14  
A2  
A1  
A0  
I/O  
I/O8–I/O15  
9
I/O  
13  
I/O  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
2
I/O  
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
3
12  
V
CC  
SS  
V
SS  
I/O  
V
CC  
I/O  
4
11  
10  
I/O  
I/O  
5
I/O  
I/O  
I/O  
6
9
COLUMN DECODER  
I/O  
7
8
WE  
A
NC  
A
BHE  
WE  
CE  
4
14  
8
A
A
9
A
A
A
13  
12  
10  
11  
OE  
A
BLE  
NC  
NC  
Notes  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com  
2. NC pins are not connected on the die.  
Cypress Semiconductor Corporation  
Document #: 38-05461 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised November 8, 2006  
[+] Feedback  
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