Datasheet > CY7C1020D_11

CY7C1020D_11

更新时间： 2024-02-05 15:46:17

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
15页	444K
描述
512K (32K x 16) Static RAM Automatic power-down when deselected

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CY7C1020D_11 数据手册

CY7C1020D

512K (32K x 16) Static RAM

Features

Functional Description ^[1]

■ Pin- and function-compatible with CY7C1020B

The CY7C1020D is a high-performance CMOS static RAM

organized as 32,768 words by 16 bits. This device has an

automatic power-down feature that significantly reduces power

consumption when deselected.The input and output pins

(IO₀through IO₁₅) are placed in a high-impedance state when:

■ High speed

— t_AA= 10 ns

■ Low active power

■ Deselected (CE HIGH)

— I_CC= 80 mA @ 10ns

■ Outputs are disabled (OE HIGH)

■ Low complementary metal oxide semiconductor (CMOS)

■ BHE and BLE are disabled (BHE, BLE HIGH)

■ When the write operation is active (CE LOW, and WE LOW)

standby power

— I_SB2= 3 mA

Write to the device by taking Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from IO pins (IO₀through IO₇), is written into the location

specified on the address pins (A₀through A₁₄). If Byte High

■ 2.0 V data retention

■ Automatic power-down when deselected

■ CMOS for optimum speed/power

■ Independent control of upper and lower bits

Enable (BHE) is LOW, then data from IO pins (IO₈through IO₁₅

)

is written into the location specified on the address pins (A₀

through A₁₄).

■ Available in Pb-free 44-pin 400-Mil wide Molded SOJ and

44-pin thin small outline package (TSOP) II packages

Reading from the device by taking Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appears on IO₀to IO₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on IO₈to IO₁₅. See the “Truth Table” on page 9 for a

complete description of read and write modes.

Logic Block Diagram

DATA IN DRIVERS

32K x 16

IO –IO

RAM Array

IO –IO

COLUMN DECODER

BHE

BLE

Note

1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05463 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 7, 2011

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与CY7C1020D_11相关器件

型号	品牌	获取价格	描述	数据表
CY7C1020D-10VXI	CYPRESS	获取价格	512K (32K x 16) Static RAM
CY7C1020D-10VXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1020D-10VXIT	CYPRESS	获取价格	Standard SRAM, 32KX16, 10ns, CMOS, PDSO44,
CY7C1020D-10VXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1020D-10ZSXI	CYPRESS	获取价格	512K (32K x 16) Static RAM
CY7C1020D-10ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1020D-10ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1020D-10ZXC	CYPRESS	获取价格	Standard SRAM, 32KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1020D-10ZXI	CYPRESS	获取价格	Standard SRAM, 32KX16, 10ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY7C1020D-12VXI	CYPRESS	获取价格	Standard SRAM, 32KX16, 12ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, SOJ-44

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