CY7C1020D
512-Kbit (32 K × 16) Static RAM
512-Kbit (32
K × 16) Static RAM
■ Deselected (CE HIGH)
Features
■ Outputs are disabled (OE HIGH)
■ Pin- and function-compatible with CY7C1020B
■ BHE and BLE are disabled (BHE, BLE HIGH)
■ When the write operation is active (CE LOW, and WE LOW)
■ High speed
❐ tAA = 10 ns
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO0 through IO7), is written into the location
specified on the address pins (A0 through A14). If Byte High
■ Low active power
❐ ICC = 80 mA @ 10 ns
■ Low complementary metal oxide semiconductor (CMOS)
standby power
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15
)
is written into the location specified on the address pins (A0
through A14).
❐ ISB2 = 3 mA
■ 2.0 V data retention
Reading from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO0 to IO7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO8 to IO15. See the “Truth Table” on page 11 for a
complete description of read and write modes.
■ Automatic power-down when deselected
■ CMOS for optimum speed/power
■ Independent control of upper and lower bits
■ Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin thin small outline package (TSOP) II packages
The CY7C1020D device is suitable for interfacing with
processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
Functional Description
[1]
The CY7C1020D
is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.The input and output pins
(IO0 through IO15) are placed in a high-impedance state when:
For a complete list of related documentation, click here.
Logic Block Diagram
DATA IN DRIVERS
A
A
7
6
5
4
A
32K x 16
A
A
A
A
A
IO –IO
0
7
RAM Array
3
2
1
0
IO –IO
8
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 38-05463 Rev. *J
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 28, 2014