CY7C1020CV33
32K x 16 Static RAM
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A14). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A14).
Features
• Pin- and function-compatible with CY7C1020V33
• High speed
— tAA = 10, 12, 15 ns
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
• CMOS for optimum speed/power
• Low active power
— 360 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Functional Description
The CY7C1020CV33 is a high-performance CMOS static
RAM organized as 32,768 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
The CY7C1020CV33 is available in standard 44-pin TSOP
Type II packages.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
Logic Block Diagram
Pin Configuration
TSOP II
DATA IN DRIVERS
Top View
44
1
NC
A
5
43
42
41
40
39
38
A
A
2
A
2
3
4
5
6
3
6
A
7
A
A
A
7
6
5
4
OE
A
1
BHE
BLE
I/O
I/O
I/O
A
0
32K × 16
CE
A
A
A
A
I/O –I/O
RAM Array
I/O
1
8
7
1
16
37
36
35
34
33
3
2
I/O
I/O
8
2
3
15
14
13
I/O –I/O
9
9
16
10
11
12
13
I/O
V
SS
I/O
1
0
4
CC
V
SS
A
V
V
CC
32
I/O
I/O
I/O
5
6
7
8
12
11
31
30
29
28
I/O
I/O
I/O
14
15
16
I/O
I/O
10
9
COLUMN DECODER
WE 17
A4
NC
18
27
26
25
A
8
BHE
19
A
A
14
13
9
10
11
WE
CE
OE
A
20
21
22
A
A
A
12
24
23
NC
NC
BLE
Selection Guide
1020CV33-10
1020CV33-12
1020CV33-15
Unit
ns
Maximum Access Time
10
90
5
12
85
5
15
80
5
Maximum Operating Current
Maximum CMOS Standby Current
mA
mA
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05133 Rev. *B
Revised August 13, 2002