Datasheet > CY62256VLL-70SNXCT

CY62256VLL-70SNXCT

更新时间： 2024-09-11 04:30:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器光电二极管
页数	文件大小	规格书
12页	423K
描述
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28

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CY62256V

256K (32K x 8) Static RAM

Features

Functional Description^[1]

• High Speed

The CY62256V family is composed of two high-performance

CMOS static RAM’s organized as 32K words by 8 bits. Easy

memory expansion is provided by an active LOW chip enable

(CE) and active LOW output enable (OE) and Tri-state drivers.

These devices have an automatic power-down feature,

reducing the power consumption by over 99% when

deselected.

— 70 ns

• Temperature Ranges

— Commercial: 0°C to 70°C

— Industrial: –40°C to 85°C

— Automotive: –40°C to 125°C

• Low voltage range:

An active LOW write enable signal (WE) controls the

writing/reading operation of the memory. When CE and WE

inputs are both LOW, data on the eight data input/output pins

(I/O₀through I/O₇) is written into the memory location

addressed by the address present on the address pins (A₀

through A₁₄). Reading the device is accomplished by selecting

the device and enabling the outputs, CE and OE active LOW,

while WE remains inactive or HIGH. Under these conditions,

the contents of the location addressed by the information on

address pins are present on the eight data input/output pins.

— 2.7V – 3.6V

• Low active power and standby power

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/power

The input/output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and write enable

(WE) is HIGH.

• Available in a Pb-free and non Pb-free standard 28-pin

narrow SOIC, 28-pin TSOP-1 and 28-pin Reverse

TSOP-1 packages

Logic Block Diagram

I/O

INPUTBUFFER

32K × 8

ARRAY

POWER

DOWN

COLUMN

DECODER

I/O

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05057 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 25, 2006

12 3 4 5 6 7...12

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与CY62256VLL-70SNXCT相关器件

型号	品牌	获取价格	描述	数据表
CY62256VLL-70SNXE	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256VLL-70SNXET	CYPRESS	获取价格	Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28
CY62256VLL-70SNXI	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256VLL-70SNXI	ROCHESTER	获取价格	32KX8 STANDARD SRAM, 70ns, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28
CY62256VLL-70SNXIT	CYPRESS	获取价格	Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28
CY62256VLL-70ZC	CYPRESS	获取价格	32K x 8 Static RAM
CY62256VLL-70ZC	ROCHESTER	获取价格	32KX8 STANDARD SRAM, 70ns, PDSO28, 8 X 13.40 MM, TSOP1-28
CY62256VLL-70ZCT	CYPRESS	获取价格	Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, TSOP1-28
CY62256VLL-70ZE	CYPRESS	获取价格	32K x 8 Static RAM
CY62256VLL-70ZET	CYPRESS	获取价格	Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, TSOP1-28

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