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CY62256VLL-70ZRE PDF预览

CY62256VLL-70ZRE

更新时间: 2024-11-24 22:08:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 389K
描述
32K x 8 Static RAM

CY62256VLL-70ZRE 数据手册

 浏览型号CY62256VLL-70ZRE的Datasheet PDF文件第2页浏览型号CY62256VLL-70ZRE的Datasheet PDF文件第3页浏览型号CY62256VLL-70ZRE的Datasheet PDF文件第4页浏览型号CY62256VLL-70ZRE的Datasheet PDF文件第5页浏览型号CY62256VLL-70ZRE的Datasheet PDF文件第6页浏览型号CY62256VLL-70ZRE的Datasheet PDF文件第7页 
CY62256V  
256K (32K x 8) Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• Speed: 70 ns and 100 ns  
• Low voltage range:  
The CY62256V family is composed of two high-performance  
CMOS static RAM’s organized as 32K words by 8 bits. Easy  
memory expansion is provided by an active LOW chip enable  
(CE) and active LOW output enable (OE) and three-state  
drivers. These devices have an automatic power-down  
feature, reducing the power consumption by over 99% when  
deselected.  
An active LOW write enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins are present on the eight data input/output pins.  
— CY62256V (2.7V–3.6V)  
— CY62256V25 (2.3V–2.7V)  
• Low active power and standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Package available in a standard 450-mil-wide (300-mil  
body width) 28-lead narrow SOIC, 28-lead TSOP-1, and  
reverse 28-lead TSOP-1 package  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH.  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
INPUTBUFFER  
A
10  
A
9
A
8
A
7
A
6
512 × 512  
ARRAY  
A
5
A
4
3
2
A
A
CE  
POWER  
DOWN  
COLUMN  
WE  
DECODER  
I/O  
7
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05057 Rev. *D  
Revised June 28, 2004  

CY62256VLL-70ZRE 替代型号

型号 品牌 替代类型 描述 数据表
CY62256VLL-70ZRXIT CYPRESS

功能相似

Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, LEAD FREE, REVERSE, TSOP1-28
CY62256VLL-70ZRXI CYPRESS

功能相似

256K (32K x 8) Static RAM
CY62256VLL-70ZRI CYPRESS

功能相似

32K x 8 Static RAM

与CY62256VLL-70ZRE相关器件

型号 品牌 获取价格 描述 数据表
CY62256VLL-70ZRET CYPRESS

获取价格

Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, REVERSE, TSOP1-28
CY62256VLL-70ZRI CYPRESS

获取价格

32K x 8 Static RAM
CY62256VLL-70ZRI ROCHESTER

获取价格

32KX8 STANDARD SRAM, 70ns, PDSO28, 8 X 13.40 MM, REVERSE, TSOP1-28
CY62256VLL-70ZRIT CYPRESS

获取价格

Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, REVERSE, TSOP1-28
CY62256VLL-70ZRXE ROCHESTER

获取价格

32KX8 STANDARD SRAM, 70ns, PDSO28, 8 X 13.40 MM, LEAD FREE, REVERSE, TSOP1-28
CY62256VLL-70ZRXE CYPRESS

获取价格

256K (32K x 8) Static RAM
CY62256VLL-70ZRXET CYPRESS

获取价格

Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, LEAD FREE, REVERSE, TSOP1-28
CY62256VLL-70ZRXI CYPRESS

获取价格

256K (32K x 8) Static RAM
CY62256VLL-70ZRXIT CYPRESS

获取价格

Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, LEAD FREE, REVERSE, TSOP1-28
CY62256VLL-70ZXC CYPRESS

获取价格

256K (32K x 8) Static RAM