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CY62256VLL-70SNXET PDF预览

CY62256VLL-70SNXET

更新时间： 2024-09-10 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 438K
描述
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28

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CY62256VLL-70SNXET 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：28
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.63
Is Samacsys：N最长访问时间：70 ns
JESD-30 代码：R-PDSO-G28JESD-609代码：e4
长度：17.9324 mm内存密度：262144 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
功能数量：1端子数量：28
字数：32768 words字数代码：32000
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-40 °C组织：32KX8
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：2.794 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：7.5057 mm
Base Number Matches：1

CY62256VLL-70SNXET 数据手册

 浏览型号CY62256VLL-70SNXET的Datasheet PDF文件第2页浏览型号CY62256VLL-70SNXET的Datasheet PDF文件第3页浏览型号CY62256VLL-70SNXET的Datasheet PDF文件第4页浏览型号CY62256VLL-70SNXET的Datasheet PDF文件第5页浏览型号CY62256VLL-70SNXET的Datasheet PDF文件第6页浏览型号CY62256VLL-70SNXET的Datasheet PDF文件第7页 
CY62256V  
256K (32K x 8) Static RAM  
Features  
Functional Description[1]  
• High Speed  
The CY62256V family is composed of two high-performance  
CMOS static RAM’s organized as 32K words by 8 bits. Easy  
memory expansion is provided by an active LOW chip enable  
(CE) and active LOW output enable (OE) and Tri-state drivers.  
These devices have an automatic power-down feature,  
reducing the power consumption by over 99% when  
deselected.  
— 70 ns  
• Temperature Ranges  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• Low voltage range:  
An active LOW write enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins are present on the eight data input/output pins.  
— 2.7V – 3.6V  
• Low active power and standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH.  
• Available in a Pb-free and non Pb-free standard 28-pin  
narrow SOIC, 28-pin TSOP-1 and 28-pin Reverse  
TSOP-1 packages  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
INPUTBUFFER  
A
A
A
10  
9
8
A
7
6
5
32K × 8  
ARRAY  
A
A
A
A
A
4
3
2
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05057 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 25, 2006  
[+] Feedback  
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CY62256VLL-70SNXI ROCHESTER

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CY62256VLL-70SNXIT CYPRESS

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CY62256VLL-70ZC ROCHESTER

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CY62256VLL-70ZCT CYPRESS

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 		Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, TSOP1-28
CY62256VLL-70ZE CYPRESS

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 		32K x 8 Static RAM
CY62256VLL-70ZET CYPRESS

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 		Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, TSOP1-28
CY62256VLL-70ZI CYPRESS

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 		32K x 8 Static RAM
CY62256VLL-70ZI ROCHESTER

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 		32KX8 STANDARD SRAM, 70ns, PDSO28, 8 X 13.40 MM, TSOP1-28

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