Datasheet > CY62138EV30

CY62138EV30

更新时间： 2024-11-24 04:53:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
9页	486K
描述
2-Mbit (256K x 8) MoBL㈢ Static RAM

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CY62138EV30 数据手册

CY62138EV30

MoBL^®

2-Mbit (256K x 8) MoBL^®Static RAM

Features

Functional Description^[1]

• Very high speed: 45 ns

The CY62138EV30 is a high-performance CMOS static RAM

organized as 256K words by 8 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly

reduces power consumption. The device can be put into

standby mode reducing power consumption when deselected

(CE HIGH).

— Wide voltage range: 2.20V – 3.60V

• Pin-compatible with CY62138CV30

• Ultra-low standby power

— Typical standby current: 1 µA

— Maximum standby current: 7 µA

• Ultra-low active power

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location

— Typical active current: 2 mA @ f = 1 MHz

• Easy memory expansion with CE and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

specified on the address pins (A₀through A₁₈).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

• Offered in Pb-free 36-ball BGA package

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW and WE LOW).

Logic Block Diagram

I/O

Data in Drivers

A₀

A₁

A²₃

A₄

A⁵

256K x 8

ARRAY

A⁶

A₈⁷

A₉

A₁₀

A₁₁

POWER

DOWN

COLUMN

DECODER

I/O

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05577 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 14, 2006

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与CY62138EV30相关器件

型号	品牌	获取价格	描述	数据表
CY62138EV30_09	CYPRESS	获取价格	2-Mbit (256K x 8) MoBL Static RAM
CY62138EV30_11	CYPRESS	获取价格	2 Mbit (256K x 8) MoBL Static RAM
CY62138EV30_1106	CYPRESS	获取价格	2-Mbit (256 K x 8) MoBL Static RAM Automatic power down when deselected
CY62138EV30_12	CYPRESS	获取价格	2-Mbit (256 K Ã 8) MoBL Static RAM
CY62138EV30LL	CYPRESS	获取价格	2 Mbit (256K x 8) MoBL Static RAM
CY62138EV30LL-45BVXI	CYPRESS	获取价格	2-Mbit (256K x 8) MoBL㈢ Static RAM
CY62138EV30LL-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62138EV30LL-45BVXI_12	CYPRESS	获取价格	2-Mbit (256 K Ã 8) MoBL Static RAM
CY62138EV30LL-45BVXIT	CYPRESS	获取价格	Standard SRAM, 256KX8, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62138EV30LL-45BVXIT	INFINEON	获取价格	Asynchronous SRAM

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