Datasheet > CY62138EV30_12

CY62138EV30_12

更新时间： 2024-11-27 12:51:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
16页	494K
描述
2-Mbit (256 K Ã 8) MoBL Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62138EV30_12 数据手册

CY62138EV30 MoBL^®

2-Mbit (256 K × 8) MoBL^®Static RAM

2-Mbit (256

K × 8) MoBL^®Static RAM

Features

Functional Description

■ Very high speed: 45 ns

❐ Wide voltage range: 2.20 V to 3.60 V

The CY62138EV30 is a high performance CMOS static RAM

organized as 256K words by eight bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption. The device can be put into standby mode reducing

power consumption when deselected (CE HIGH).

■ Pin compatible with CY62138CV30

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 7 A

■ Ultra low active power

❐ Typical active current: 2 mA at f = 1 MHz

Writing to the device is accomplished by taking Chip Enable (CE)

and Write Enable (WE) inputs LOW. Data on the eight I/O pins

(I/O₀through I/O₇) is then written into the location specified on

the address pins (A₀through A₁₈).

■ Easy memory expansion with CE and OE features

■ Automatic power down when deselected

Reading from the device is accomplished by taking Chip Enable

(CE) and Output Enable (OE) LOW while forcing Write Enable

(WE) HIGH. Under these conditions, the contents of the memory

location specified by the address pins appear on the I/O pins.

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

■ Offered in Pb-free 36-ball ball grid array (BGA) package

The eight input and output pins (I/O₀through I/O₇) are placed in

a high impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW and WE LOW).

Logic Block Diagram

I/O

Data in Drivers

A₀

A₁

A²₃

A₄

A₅

256K x 8

ARRAY

A⁶

A₈⁷

A₉

A₁₀

A₁₁

POWER

DOWN

COLUMN

DECODER

I/O

Cypress Semiconductor Corporation

Document Number: 38-05577 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 8, 2012

12 3 4 5 6 7...16

中文翻译

下载PDF

与CY62138EV30_12相关器件

型号	品牌	获取价格	描述	数据表
CY62138EV30LL	CYPRESS	获取价格	2 Mbit (256K x 8) MoBL Static RAM
CY62138EV30LL-45BVXI	CYPRESS	获取价格	2-Mbit (256K x 8) MoBL㈢ Static RAM
CY62138EV30LL-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62138EV30LL-45BVXI_12	CYPRESS	获取价格	2-Mbit (256 K Ã 8) MoBL Static RAM
CY62138EV30LL-45BVXIT	CYPRESS	获取价格	Standard SRAM, 256KX8, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62138EV30LL-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62138F	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138F_09	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138F_10	CYPRESS	获取价格	2-Mbit (256K x 8) Static RAM
CY62138F_11	CYPRESS	获取价格	2-Mbit (256 K x 8) Static RAM Automatic power down when deselected

与CY62138EV30_12相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

46
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

34
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

63
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

60

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62138EV30_12

CY62138EV30_12 数据手册

与CY62138EV30_12相关器件

与CY62138EV30_12相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62138EV30_12

CY62138EV30_12 数据手册

与CY62138EV30_12相关器件

与CY62138EV30_12相关文章

您还可以找

您在本页遇到什么问题？