Datasheet > CY3670

CY3670

更新时间： 2024-11-05 22:10:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器可编程只读存储器电动程控只读存储器
页数	文件大小	规格书
8页	121K
描述
Single-PLL General-Purpose EPROM Programmable Clock Generator

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中文翻译

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数据手册

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CY3670 数据手册

CY2071A

Single-PLL General-Purpose

EPROM Programmable Clock Generator

Features

Single phase-locked loop architecture

EPROM programmability

Benefits

Generates a custom frequency from an external source

Easy customization and fast turnaround

Factory-programmable (CY2071A, CY2071AI) or field- Programming support available for all opportunities

programmable (CY2071AF, CY2071AFI) device options

Up to three configurable outputs

Low-skew, low-jitter, high-accuracy outputs

Internal loop filter

Generates three related frequencies from a single device

Meets critical industry standard timing requirements

Alleviates the need for external components

Supports low-power applications

Power management (OE)

Frequency select options

3 outputs with 2 user selectable frequencies

Supports industry standard design platforms

Industry-standard packaging saves on board space

Configurable 5V or 3.3V operation

8-pin 150-mil SOIC package

Selector Guide

Part Number Outputs

Input Frequency Range

10 MHz–25 MHz (external crystal) 500 kHz–130 MHz (5V)

1 MHz–30 MHz (reference clock) 500 kHz–100 MHz (3.3V)

10 MHz–25 MHz (external crystal) 500 kHz–100 MHz (5V)

1 MHz–30 MHz (reference clock) 500 kHz–80 MHz (3.3V)

10 MHz–25 MHz (external crystal) 500 kHz–100 MHz (5V)

1 MHz–30 MHz (reference clock) 500 kHz–80 MHz (3.3V)

10 MHz–25 MHz (external crystal) 500 kHz–90 MHz (5V)

Output Frequency Range

Specifics

CY2071A

CY2071AI

CY2071AF

CY2071AFI

Factory Programmable

Commercial Temperature

Factory Programmable

Industrial Temperature

Field Programmable

Commercial Temperature

Field Programmable

1 MHz–30 MHz (reference clock)

500 kHz–66.6 MHz (3.3V)

Industrial Temperature

Logic Block Diagram for CY2071A

XTALIN

REFERENCE

OSCILLATOR

CLKA

EPROM-

Configurable

Multiplexer

and Divide

Logic

XTALOUT

PLL

Block

CLKB

CLKC

OE / FS

Pin Configuration

8-pin SOIC

Top View

OE/FS

CLKA

GND

XTALIN

CLKC

CLKB

XTALOUT

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07139 Rev. *A

Revised December 14, 2002

12 3 4 5 6 7 8

中文翻译

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