Datasheet > CY3685

CY3685

更新时间： 2024-11-06 04:13:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		闪存控制器
页数	文件大小	规格书
9页	193K
描述
EZ-USB NX2LP USB 2.0 NAND Flash Controller

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中文翻译

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数据手册

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CY3685 数据手册

CY7C68023/CY7C68024

EZ-USB NX2LP™ USB 2.0 NAND Flash Controller

• 43-mA Typical Active Current

1.0

Features

^{• Space-saving and lead-free 56-QFN package (8mm}×

• High (480-Mbps) or full (12-Mbps) speed USB support

• Both common NAND page sizes supported

— 512bytes –Up to 1Gbit Capacity

— 2K bytes –Up to 8Gbit Capacity

• 8 chip enable pins

8mm)

• Support for board-level manufacturing test via USB

interface

• 3.3V NAND Flash operation

• NAND Flash power management support

— Up to 8 NAND Flash single-device chips

— Up to 4 NAND Flash dual-device chips

• Industry standard ECC NAND Flash correction

— 1-bit per 256 correction

2.0

Introduction

The EZ-USB NX2LP (NX2LP) implements a USB 2.0 NAND

Flash controller. This controller adheres to the Mass Storage

Class Bulk-Only Transport Specification. The USB port of the

NX2LP is connected to a host computer directly or via the

downstream port of a USB hub. Host software issues

commands and data to the NX2LP and receives status and

data from the NX2LP using standard USB protocol.

— 2-bit error detection

• Industry standard (SmartMedia) page management for

wear leveling algorithm, bad block handling, and Physical

to Logical management.

• Supports 8-bit NAND Flash interfaces

The NX2LP supports industry leading 8-bit NAND Flash inter-

faces and both common NAND page sizes of 512 and 2k

bytes. Eight chip enable pins allow the NX2LP to be connected

to up to eight single- or four dual-device NAND Flash chips.

• Supports 30ns, 50ns, 100ns NAND Flash timing

• Complies with USB Mass Storage Class Specification rev

1.0

• CY7C68024 complies with USB 2.0 Specification for Bus-

Powered Devices (TID# 40460274)

Certain NX2LP features are configurable, enabling the NX2LP

to meet the needs of different designs’ requirements.

Write Protect

LED2#

Chip Reset

LED1#

24 MHz

PLL

Xtal

EZ-USB NX2LP

Internal Control Logic

Control

NAND Control Signals

Chip Enable Signals

8-bit Data Bus

NAND Flash

Interface

Logic

Smart HS/

FS USB

Engine

VBUS

D+

D-

USB 2.0

Xceiver

Data

Figure 1-1. NX2LP Block Diagram

Cypress Semiconductor Corporation

Document #: 38-08055 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised March 16, 2005

12 3 4 5 6 7...9

中文翻译

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