Datasheet > CY3687

CY3687

更新时间： 2024-09-16 04:13:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		微控制器
页数	文件大小	规格书
39页	1093K
描述
MoBL-USB⑩ FX2LP18 USB Microcontroller

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中文翻译

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数据手册

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CY3687 数据手册

CY7C68053

MoBL-USB™ FX2LP18 USB

Microcontroller

1. CY7C68053 Features

■ USB 2.0 – USB-IF High-Speed and Full-Speed Compliant

(TID# 40000188)

■ Integrated, industry standard enhanced 8051

❐ 48 MHz, 24 MHz, or 12 MHz CPU operation

❐ Four clocks per instruction cycle

❐ Three counter/timers

❐ Expanded interrupt system

❐ Two data pointers

■ Single-chip integrated USB 2.0 transceiver, smart SIE, and

enhanced 8051 microprocessor

■ Ideal for mobile applications (cell phone, smart phones,

PDAs, MP3 players)

❐ Ultra low power

■ 1.8V Core operation

❐ Suspend current: 20 µA (typical)

■ 1.8V - 3.3V IO operation

■ Software: 8051 code runs from:

❐ Internal RAM, which is loaded from EEPROM

■ Vectored USB interrupts and GPIF/FIFO interrupts

■ Separate data buffers for the Setup and Data portions of a

CONTROL transfer

■ 16 kBytes of on-chip Code/Data RAM

■ Integrated I²C™ controller, runs at 100 or 400 kHz

■ Four programmable BULK/INTERRUPT/ISOCHRONOUS

endpoints

❐ Buffering options: double, triple, and quad

■ Four integrated FIFOs

❐ Integrated glue logic and FIFOs lower system cost

❐ Automatic conversion to and from 16-bit buses

❐ Master or slave operation

■ Additional programmable (BULK/INTERRUPT) 64-byte

endpoint

■ 8- or 16-bit external data interface

❐ Uses external clock or asynchronous strobes

❐ Easy interface to ASIC and DSP ICs

■ Smart Media Standard ECC generation

■ Available in Industrial temperature grade

■ GPIF (General Programmable Interface)

■ Available in one Pb-free package with up to 24 GPIOs

❐ 56-pin VFBGA (24 GPIOs)

❐ Allows direct connection to most parallel interface

❐ Programmable waveform descriptors and configuration reg-

isters to define waveforms

❐ Supports multiple Ready and Control outputs

High-performance microprocessor

using standard tools

Block Diagram

24 MHz

Ext. XTAL

with lower-power options

MoBL-USB FX2LP18

/0.5

/1.0

/2.0

8051 Core

12/24/48 MHz,

Four Clocks/Cycle

x20

PLL

Master

VCC

Abundant IO

Additional IOs (24)

1.5K

Connected for

Full-Speed

D+

D–

General

Programmable I/F

To Baseband Processors/

Application Processors/

ASICS/DSPs

GPIF

USB

2.0

XCVR

Smart

USB

1.1/2.0

Engine

16 KB

RAM

RDY (2)

CTL (3)

ECC

Integrated

Full- and High-Speed

XCVR

Up to 96 MBytes/sec

Burst Rate

4 KB

FIFO

8/16

Enhanced USB Core

Simplifies 8051 Code

“Soft Configuration”

Easy Firmware Changes

FIFO and Endpoint Memory

(Master or Slave Operation)

Cypress Semiconductor Corporation

Document # 001-06120 Rev *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 6, 2007

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与CY3687相关器件

型号	品牌	获取价格	描述	数据表
CY3690	CYPRESS	获取价格	PTG Programming Kit
CY3691	CYPRESS	获取价格	PTG Programming Kit
CY3692	CYPRESS	获取价格	200-MHz Field Programmable Zero Delay Buffer
CY3693	CYPRESS	获取价格	PTG Programming Kit
CY3694	CYPRESS	获取价格	PTG Programming Kit
CY3695	CYPRESS	获取价格	PTG Programming Kit
CY3696	CYPRESS	获取价格	PTG Programming Kit
CY3697	CYPRESS	获取价格	PTG Programming Kit
CY3698	CYPRESS	获取价格	PTG Programming Kit
CY3699	CYPRESS	获取价格	PTG Programming Kit

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