Datasheet > CY3692

CY3692

更新时间： 2024-09-15 22:10:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	203K
描述
200-MHz Field Programmable Zero Delay Buffer

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CY3692 数据手册

CY23FP12

200-MHz Field Programmable Zero Delay Buffer

Features

Functional Description

• Fully field-programmable

— Input and output dividers

— Inverting/noninverting outputs

The CY23FP12 is a high-performance fully field-program-

mable 200 MHz zero delay buffer designed for high speed

clock distribution. The integrated PLL is designed for low jitter

and optimized for noise rejection. These parameters are

critical for reference clock distribution in systems using

high-performance ASICs and microprocessors.

— Phase-locked loop (PLL) or fanout buffer configu-

ration

The CY23FP12 is fully programmable via volume or prototype

programmers enabling the user to define an appli-

cation-specific Zero Delay Buffer with customized input and

output dividers, feedback topology (internal/external), output

inversions, and output drive strengths. For additional flexibility,

the user can mix and match multiple functions, listed in

Table 2, and assign a particular function set to any one of the

four possible S1-S2 control bit combinations. This feature

allows for the implementation of four distinct personalities,

selectable with S1-S2 bits, on a single programmed silicon.

The CY23FP12 also features a proprietary auto-power-down

circuit that shuts down the device in case of a REF failure,

resulting in less than 50 µA of current draw.

• 10-MHz to 200-MHz operating range

• Split 2.5V or 3.3V outputs

• Two LVCMOS reference inputs

• Twelve low-skew outputs

— 35ps typ. output-to-output skew (same freq)

• 110 ps typ. cycle-cycle jitter (same freq)

• Three-stateable outputs

• < 50-µA shutdown current

• Spread Aware

• 28-pin SSOP

The CY23FP12 provides twelve outputs grouped in two banks

with separate power supply pins which can be connected

independently to either a 2.5V or a 3.3V rail.

• 3.3V operation

• Industrial temperature available

Selectable reference input is a fault tolerance feature which

allows for glitch-free switch over to secondary clock source

when REFSEL is asserted/deasserted.

Pin Configuration

Block Diagram

SSOP

VDDA

VDDC

Top View

CLKA0

CLKA1

CLKA2

CLKA3

CLKA4

Lock Detect

REF2

REF1

REFSEL

FBK

CLKA0

CLKA1

CLKB0

CLKB1

V_SSA

V_SSB

CLKB2

REFSEL

REF1

CLKA2

CLKA3

V_DDA

CLKA5

VSSA

VDDB

÷M

÷N

100 to

400MHz

PLL

CLKB3

÷1

÷2

÷3

÷4

÷X

REF2

V_DDB

FBK

V_SSA

V_SSB

CLKB4

CLKB5

CLKA4

CLKA5

V_DDA

V_SSC

CLKB0

CLKB1

CLKB2

CLKB3

CLKB4

V_DDB

V_DDC

Test Logic

Function

Selection

S[2:1]

VSSC

CLKB5

VSSB

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07246 Rev. *E

Revised December 13, 2004

12 3 4 5 6 7...10

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