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CY3674

更新时间: 2024-11-06 04:13:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 微控制器
页数 文件大小 规格书
50页 758K
描述
EZ-USB FX1⑩ USB Microcontroller Full-speed USB Peripheral Controller

CY3674 数据手册

 浏览型号CY3674的Datasheet PDF文件第2页浏览型号CY3674的Datasheet PDF文件第3页浏览型号CY3674的Datasheet PDF文件第4页浏览型号CY3674的Datasheet PDF文件第5页浏览型号CY3674的Datasheet PDF文件第6页浏览型号CY3674的Datasheet PDF文件第7页 
CY7C64713/14  
EZ-USB FX1™ USB Microcontroller  
Full-speed USB Peripheral Controller  
Supports multiple Ready (RDY) inputs and Control  
(CTL) outputs  
• Integrated, industry standard 8051 with enhanced  
features  
1.0  
Features  
• Single-chip integrated USB transceiver, SIE, and  
enhanced 8051 microprocessor  
• Fit, form and function upgradable to the FX2LP  
(CY7C68013A)  
Up to 48-MHz clock rate  
Four clocks per instruction cycle  
Two USARTS  
Three counter/timers  
Expanded interrupt system  
Two data pointers  
— Pin-compatible  
— Object-code-compatible  
— Functionally-compatible (FX1 functionality is a  
Subset of the FX2LP)  
• Draws no morethan65 mA in any mode making theFX1  
suitable for bus powered applications  
• 3.3V operation with 5V tolerant inputs  
• Smart SIE  
• Software: 8051 runs from internal RAM, which is:  
— Downloaded via USB  
— Loaded from EEPROM  
— Externalmemorydevice(128-pinconfigurationonly)  
• 16 KBytes of on-chip Code/Data RAM  
• Vectored USB interrupts  
Separate data buffers for the Setup and DATA portions  
of a CONTROL transfer  
Integrated I2C controller, runs at 100 or 400 KHz  
48-MHz, 24-MHz, or 12-MHz 8051 operation  
Four integrated FIFOs  
• Four programmable BULK/INTERRUPT/ISOCH-  
RONOUS endpoints  
Brings glue and FIFOs inside for lower system cost  
Automatic conversion to and from 16-bit buses  
Master or slave operation  
— Buffering options: double, triple, and quad  
• Additional programmable (BULK/INTERRUPT) 64-byte  
endpoint  
• 8- or 16-bit external data interface  
• Smart Media Standard ECC generation  
• GPIF  
FIFOs can use externally supplied clock or  
asynchronous strobes  
Easy interface to ASIC and DSP ICs  
Vectored for FIFO and GPIF interrupts  
Up to 40 general purpose I/Os  
— Allowsdirect connection to most parallel interfaces;  
8- and 16-bit  
Three package options128-pin TQFP, 100-pin TQFP,  
and 56-pin QFN Lead-free  
— Programmable waveform descriptors and configu-  
ration registers to define waveforms  
High-performance micro  
using standard tools  
24 MHz  
Ext. XTAL  
with lower-power options  
FX1  
I2C  
/0.5  
/1.0  
/2.0  
8051 Core  
x20  
Master  
VCC  
12/24/48 MHz,  
four clocks/cycle  
PLL  
Abundant I/O  
Additional I/Os (24)  
1.5k  
connected for  
enumeration  
including two USARTS  
General  
ADDR (9)  
programmable I/F  
to ASIC/DSP or bus  
standards such as  
D+  
GPIF  
USB  
CY  
16 KB  
RAM  
RDY (6)  
CTL (6)  
ATAPI, EPP, etc.  
D–  
ECC  
Smart  
XCVR  
USB  
Engine  
Integrated  
full-speed XCVR  
Up to 96 MBytes/s  
burst rate  
4 kB  
FIFO  
8/16  
Enhanced USB core  
Simplifies 8051 code  
Soft Configuration”  
Easy firmware changes  
FIFO and endpoint memory  
(master or slave operation)  
Figure 1-1. Block Diagram  
Cypress Semiconductor Corporation  
Document #: 38-08039 Rev. *B  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised February 14, 2005  

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