Datasheet > CY3684

CY3684

更新时间： 2024-09-16 04:13:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		微控制器
页数	文件大小	规格书
60页	3344K
描述
EZ-USB FX2LP⑩ USB Microcontroller

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中文翻译

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数据手册

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CY3684 数据手册

CY7C68013A/CY7C68014A

CY7C68015A/CY7C68016A

EZ-USB FX2LP™ USB Microcontroller

— Programmable waveform descriptors and configu-

1.0

Features (CY7C68013A/14A/15A/16A)

ration registers to define waveforms

• USB 2.0–USB-IF high speed certified (TID # 40440111)

—Supports multiple Ready (RDY) inputs and Control

(CTL) outputs

• Single-chip integrated USB 2.0 transceiver, smart SIE,

and enhanced 8051 microprocessor

• Integrated, industry-standard enhanced 8051

—48-MHz, 24-MHz, or 12-MHz CPU operation

—Four clocks per instruction cycle

— Two USARTS

• Fit, form and function compatible with the FX2

— Pin-compatible

— Object-code-compatible

— Functionally-compatible (FX2LP is a superset)

• Ultra Low power: I_CCno more than 85 mA in any mode

— Three counter/timers

— Expanded interrupt system

—Two data pointers

—Ideal for bus and battery powered applications

• Software: 8051 code runs from:

• 3.3V operation with 5V tolerant inputs

• Vectored USB interrupts and GPIF/FIFO interrupts

— Internal RAM, which is downloaded via USB

—Internal RAM, which is loaded from EEPROM

— External memory device (128 pin package)

• 16 KBytes of on-chip Code/Data RAM

• Separate data buffers for the Set-up and Data portions

of a CONTROL transfer

• Integrated I²C controller, runs at 100 or 400 kHz

• Four integrated FIFOs

• Four programmable BULK/INTERRUPT/ISOCHRO-

NOUS endpoints

— Integrated glue logic and FIFOs lower system cost

— Automatic conversion to and from 16-bit buses

— Master or slave operation

—Buffering options: double, triple, and quad

• Additional programmable (BULK/INTERRUPT) 64-byte

endpoint

— Uses external clock or asynchronous strobes

— Easy interface to ASIC and DSP ICs

• 8- or 16-bit external data interface

• Smart Media Standard ECC generation

• GPIF (General Programmable Interface)

— Allows direct connection to most parallel interface

• Available in Commercial and Industrial temperature

grade (all packages except VFBGA)

High-performance micro

using standard tools

24 MHz

Ext. XTAL

with lower-power options

FX2LP

/0.5

/1.0

/2.0

I C

8051 Core

x20

Master

VCC

12/24/48 MHz,

four clocks/cycle

PLL

Abundant I/O

including two USARTS

Additional I/Os (24)

1.5k

connected for

full speed

General

ADDR (9)

programmable I/F

to ASIC/DSP or bus

standards such as

D+

D–

GPIF

USB

2.0

XCVR

Smart

USB

16 KB

RAM

RDY (6)

CTL (6)

ATAPI, EPP, etc.

ECC

1.1/2.0

Engine

Integrated

full- and high-speed

XCVR

Up to 96 MBytes/s

burst rate

4 kB

FIFO

8/16

Enhanced USB core

Simplifies 8051 code

“Soft Configuration”

Easy firmware changes

FIFO and endpoint memory

(master or slave operation)

Figure 1-1. Block Diagram

Cypress Semiconductor Corporation

Document #: 38-08032 Rev. *K

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 26, 2006

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与CY3684相关器件

型号	品牌	获取价格	描述	数据表
CY3685	CYPRESS	获取价格	EZ-USB NX2LP USB 2.0 NAND Flash Controller
CY3686	CYPRESS	获取价格	EZ-USB NX2LP-Flex⑩ Flexible USB NAND Flash Co
CY3687	CYPRESS	获取价格	MoBL-USB⑩ FX2LP18 USB Microcontroller
CY3690	CYPRESS	获取价格	PTG Programming Kit
CY3691	CYPRESS	获取价格	PTG Programming Kit
CY3692	CYPRESS	获取价格	200-MHz Field Programmable Zero Delay Buffer
CY3693	CYPRESS	获取价格	PTG Programming Kit
CY3694	CYPRESS	获取价格	PTG Programming Kit
CY3695	CYPRESS	获取价格	PTG Programming Kit
CY3696	CYPRESS	获取价格	PTG Programming Kit

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