CY3672

更新时间： 2024-11-05 21:54:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器闪存
页数	文件大小	规格书
9页	158K
描述
One-PLL General Purpose Flash Programmable Clock Generator

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中文翻译

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CY3672 数据手册

CY22050

One-PLL General Purpose

Flash Programmable Clock Generator

Features

Benefits

• Integrated phase-locked loop (PLL)

Internal PLL to generate six outputs up to 200 MHz. Able to generate

custom frequencies from an external reference crystal or a driven source.

• Commercial and Industrial operation

• Flash-programmable

Performance guaranteed for applications that require an extended temper-

ature range.

Reprogrammable technology allows easy customization, quick turnaround

on design changes and product performance enhancements, and better

inventory control. Parts can be reprogrammed up to 100 times, reducing

inventory of custom parts and providing an easy method for upgrading

existing designs.

• Field-programmable

In-house programming of samples and prototype quantities is available

using the CY3672 FTG Development Kit. Production quantities are

available through Cypress’s value-added distribution partners or by using

third party programmers from BP Microsystems, HiLo Systems, and

others.

• Low-skew, low-jitter, high-accuracy outputs

High performance suited for commercial, industrial, networking, telecomm

and other general-purpose applications.

• 3.3V operation with 2.5V output option

• 16-lead TSSOP

Application compatibility in standard and low-power systems.

Industry standard packaging saves on board space.

Part Number Outputs

Input Frequency Range

Output Frequency Range

Specifications

CY22050FC

8 MHz–30 MHz (external crystal) 80 kHz–200 MHz (3.3V)

Field-programmable

1 MHz–133 MHz (driven clock)

80 KHz–166.6 MHz (2.5V)

commercial temperature

CY22050FI

8 MHz–30 MHz (external crystal) 80 kHz–166.6 MHz (3.3V)

Field-programmable

1 MHz–133 MHz (driven clock)

80 KHz–150 MHz (2.5V)

industrial temperature

LCLK1

LCLK2

Logic Block Diagram

Divider

Bank 1

Output

LCLK3

LCLK4

Select

Matrix

XIN

XOUT

OSC.

VCO

PLL

Divider

Bank 2

CLK5

CLK6

AVSS VSS

VDD

AVDD

VDDL VSSL PWRDWN

Pin Configuration

XOUT

XIN

VDD

AVDD

PWRDWN

CLK6

CLK5

VSS

AVSS

VSSL

LCLK1

LCLK2

LCLK4

VDDL

LCLK3

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07006 Rev. *D

Revised January 29, 2005

12 3 4 5 6 7...9

中文翻译

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与CY3672相关器件

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