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CXK79M36C162GB-44 PDF预览

CXK79M36C162GB-44

更新时间： 2024-11-10 21:15:59
品牌 Logo 应用领域
索尼 - SONY 时钟静态存储器内存集成电路
页数 文件大小 规格书
25页 359K
描述
Standard SRAM, 512KX36, 2.3ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209

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CXK79M36C162GB-44 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA, BGA209,11X19,40针数：209
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
最长访问时间：2.3 ns最大时钟频率 (fCLK)：227 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B209
JESD-609代码：e0长度：22 mm
内存密度：18874368 bit内存集成电路类型：STANDARD SRAM
内存宽度：36功能数量：1
端子数量：209字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：
组织：512KX36输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA209,11X19,40封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：1.5/1.8,1.8 V
认证状态：Not Qualified座面最大高度：2.3 mm
最大待机电流：0.25 A最小待机电流：1.7 V
子类别：SRAMs最大压摆率：0.7 mA
最大供电电压 (Vsup)：1.95 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：10宽度：14 mm
Base Number Matches：1

CXK79M36C162GB-44 数据手册

 浏览型号CXK79M36C162GB-44的Datasheet PDF文件第2页浏览型号CXK79M36C162GB-44的Datasheet PDF文件第3页浏览型号CXK79M36C162GB-44的Datasheet PDF文件第4页浏览型号CXK79M36C162GB-44的Datasheet PDF文件第5页浏览型号CXK79M36C162GB-44的Datasheet PDF文件第6页浏览型号CXK79M36C162GB-44的Datasheet PDF文件第7页 
SONYÒ SRAM CXK79M36C162GB / CXK79M18C162GB 33/4/44  
16Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36 or 1Mb x 18)  
Preliminary  
Description  
The CXK79M36C162GB (organized as 524,288 words by 36 bits) and the CXK79M18C162GB (organized as 1,048,576 words  
by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. They are manufactured in compliance with  
the JEDEC-standard 209 pin BGA package pinouts defined for SigmaRAMs. They integrate input registers, high speed RAM,  
output registers, and a two-deep write buffer onto a single monolithic IC. Double Data Rate (DDR) Pipelined (PL) read opera-  
tions and Late Write (LW) write operations are supported, providing a high-performance user interface. Positive and negative  
output clocks are provided for applications requiring source-synchronous operation.  
All address and control input signals are registered on the rising edge of the CK differential input clock.  
During read operations, output data is driven valid twice, from both the rising and falling edges of CK, beginning one full cycle  
after the address and control signals are registered.  
During write operations, input data is registered twice, on both the rising and falling edges of CK, beginning one full cycle after  
the address and control signals are registered.  
Because two pieces of data are always transferred during read and write operations, the least significant address bit of the inter-  
nal memory array is not available as an external address pin to these devices. Rather, the address bit is set to “0” internally prior  
to the first data transfer, and then incremented to “1” internally prior to the second data transfer. Consequently, the two pieces  
of data transferred during read and write operations are always read in the same address sequence in which they are written.  
Output drivers are series-terminated, and output impedance is programmable via the ZQ control pin. When an external resistor  
RQ is connected between ZQ and V , the impedance of the SRAM’s output drivers is set to ~RQ/5.  
SS  
300 MHz operation (600 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using  
a subset of IEEE standard 1149.1 protocol.  
Features  
•
3 Speed Bins  
Cycle Time / Data Access Time  
3.3ns / 1.8ns  
-33  
-4  
4.0ns / 2.1ns  
-44  
4.4ns / 2.3ns  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single 1.8V power supply (V ): 1.7V (min) to 1.95V (max)  
DD  
Dedicated output supply voltage (V  
): 1.8V or 1.5V typical  
DDQ  
HSTL-compatible I/O interface with dedicated input reference voltage (V ): V  
/2 typical  
DDQ  
REF  
Common I/O  
Double Data Rate (DDR) data transfers  
Pipelined (PL) read operations  
Late Write (LW) write operations  
Burst capability with internally controlled Linear Burst address sequencing  
Burst length of two, three, or four, with automatic address wrap  
Full read/write coherency  
Two cycle deselect  
Differential input clocks (CK/CK)  
Data-referenced output clocks (CQ/CQ)  
Programmable output driver impedance via dedicated control pin (ZQ)  
Depth expansion capability (two or four banks) via programmable chip enables (E2, E3, EP2, EP3)  
JTAG boundary scan (subset of IEEE standard 1149.1)  
209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package  
16Mb 1x2Lp, HSTL, rev 0.1  
1 / 25  
July 6, 2001  
1234567...25

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与CXK79M36C162GB-44相关器件

型号 品牌 获取价格 描述 数据表
CXK79M36C162GB-5 SONY

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 		18Mb 1x2Lp HSTL High Speed Synchronous SRAMs (512Kb x 36)
CXK79M36C163GB ETC

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 		MEMORY-SigmaRAM 16Meg 1x2 LVCMOX I/O (512K x 36) (25 pages 360K Rev. 7/6/01)
CXK79M36C163GB-4 SONY

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 		Standard SRAM, 512KX36, 2.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
CXK79M36C163GB-44 SONY

获取价格

 		Standard SRAM, 512KX36, 2.3ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
CXK79M36C163GB-5 SONY

获取价格

 		Standard SRAM, 512KX36, 2.3ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
CXK79M36C164GB SONY

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 		18Mb 1x1Dp HSTL High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36)
CXK79M36C164GB-28 SONY

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 		Standard SRAM, 512KX36, 1.7ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
CXK79M36C164GB-33 SONY

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 		Standard SRAM, 512KX36, 1.9ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
CXK79M36C164GB-44 SONY

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 		Standard SRAM, 512KX36, 3.2ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
CXK79M36C164GB-5 SONY

获取价格

 		Standard SRAM, 512KX36, 2.3ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209

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