Datasheet > CXK79M36C163GB-4

CXK79M36C163GB-4

更新时间： 2024-02-26 05:46:49

品牌	Logo	应用领域
索尼 - SONY		静态存储器内存集成电路
页数	文件大小	规格书
25页	394K
描述
Standard SRAM, 512KX36, 2.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209

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技术参数
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CXK79M36C163GB-4 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA, BGA209,11X19,40	针数：	209
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	2.1 ns	其他特性：	PIPELINED ARCHITECTURE; LATE WRITE
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B209
JESD-609代码：	e0	长度：	22 mm
内存密度：	18874368 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	36	功能数量：	1
端子数量：	209	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：
组织：	512KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA209,11X19,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	2.3 mm
最小待机电流：	1.7 V	子类别：	SRAMs
最大供电电压 (Vsup)：	1.95 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	10	宽度：	14 mm
Base Number Matches：	1

CXK79M36C163GB-4 数据手册

SONY ΣRAM^™

CXK79M36C163GB

33/4/5

18Mb 1x2Lp LVCMOS High Speed Synchronous SRAMs (512Kb x 36)

Preliminary

Description

The CXK79M36C163GB is a high speed CMOS synchronous static RAM with common I/O pins. It is manufactured in com-

pliance with the JEDEC-standard 209 pin BGA package pinout defined for SigmaRAM^™devices. It integrates input registers,

high speed RAM, output registers, and a two-deep write buffer onto a single monolithic IC. Double Data Rate (DDR) Pipelined

(PL) read operations and Late Write (LW) write operations are supported, providing a high-performance user interface. Positive

and negative output clocks are provided for applications requiring source-synchronous operation.

All address and control input signals are registered on the rising edge of the CK input clock.

During read operations, output data is driven valid twice, from both the rising and falling edges of CK, beginning one full cycle

after the address and control signals are registered.

During write operations, input data is registered twice, on both the rising and falling edges of CK, beginning one full cycle after

the address and control signals are registered.

Because two pieces of data are always transferred during read and write operations, the least significant address bit of the in-

ternal memory array is not available as an external address pin to this device. Consequently, the number of external address pins

available to the device is one less than the specified depth of the device (i.e. the 512Kb x 36 device has 18, not 19, external

address pins). And, the user cannot choose the order in which the two pieces of data are read. Read data is always provided in

the same order in which it is written.

Output drivers are series-terminated, and output impedance is selectable via the ZQ control pin. When ZQ is tied “low”, the

impedance of the SRAM’s output drivers is set to ~25Ω. When ZQ is tied “high” or left unconnected, the impedance of the

SRAM’s output drivers is set to ~50Ω.

300 MHz operation (600 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using

a subset of IEEE standard 1149.1 protocol.

Features

•

3 Speed Bins

Cycle Time / Data Access Time

3.3ns / 1.8ns

-33

-4

4.0ns / 2.1ns

-5

5.0ns / 2.3ns

• Single 1.8V power supply (V_DD): 1.7V (min) to 1.95V (max)

• Dedicated output supply voltage (V_DDQ): 1.4V (min) to V_DD(max)

• LVCMOS-compatible I/O interface

• Common I/O

• Double Data Rate (DDR) data transfers

• Pipelined (PL) read operations

• Late Write (LW) write operations

• Burst capability with internally controlled Linear Burst address sequencing

• Burst length of two or four, with automatic address wrap

• Full read/write data coherency

• Single-ended input clock (CK)

• Data-referenced output clocks (CQ1, CQ1, CQ2, CQ2)

• Selectable output driver impedance via dedicated control pin (ZQ)

• Depth expansion capability (2 or 4 banks) via programmable chip enables (E2, E3, EP2, EP3)

• JTAG boundary scan (subset of IEEE standard 1149.1)

• 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

18Mb 1x2Lp, LVCMOS, rev 1.1

1 / 25

November 8, 2002

12 3 4 5 6 7...25

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与CXK79M36C163GB-4相关器件

型号	品牌	获取价格	描述	数据表
CXK79M36C163GB-44	SONY	获取价格	Standard SRAM, 512KX36, 2.3ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
CXK79M36C163GB-5	SONY	获取价格	Standard SRAM, 512KX36, 2.3ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
CXK79M36C164GB	SONY	获取价格	18Mb 1x1Dp HSTL High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36)
CXK79M36C164GB-28	SONY	获取价格	Standard SRAM, 512KX36, 1.7ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
CXK79M36C164GB-33	SONY	获取价格	Standard SRAM, 512KX36, 1.9ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
CXK79M36C164GB-44	SONY	获取价格	Standard SRAM, 512KX36, 3.2ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
CXK79M36C164GB-5	SONY	获取价格	Standard SRAM, 512KX36, 2.3ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
CXK79M36C165GB	SONY	获取价格	18Mb 1x1Dp LVCMOS High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36)
CXK79M36C165GB-3	SONY	获取价格	Standard SRAM, 512KX36, 2ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209
CXK79M36C165GB-33	SONY	获取价格	Standard SRAM, 512KX36, 2ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, PLASTIC, BGA-209

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