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CXK79M72C160GB PDF预览

CXK79M72C160GB

更新时间: 2024-11-29 23:44:43
品牌 Logo 应用领域
其他 - ETC /
页数 文件大小 规格书
30页 520K
描述
MEMORY-SigmaRAM 16Meg 1x1 HSTL I/O (256K x 72) (27 pages 364K Rev. 7/6/01)

CXK79M72C160GB 数据手册

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CXK79M72C160GB CXK79M18C160GB  
CXK79M36C160GB  
SONY ΣRAM  
33/4/5  
18Mb 1x1Lp HSTL High Speed Synchronous SRAMs (256Kb x 72 or 512Kb x 36 or 1Mb x 18)  
Preliminary  
Description  
The CXK79M72C160GB (organized as 262,144 words by 72 bits), CXK79M36C160GB (organized as 524,288 words by 36  
bits), and the CXK79M18C160GB (organized as 1,048,576 words by 18 bits) are high speed CMOS synchronous static RAMs  
with common I/O pins. They are manufactured in compliance with the JEDEC-standard 209 pin BGA package pinouts defined  
for SigmaRAMs. They integrate input registers, high speed RAM, output registers, and a two-deep write buffer onto a single  
monolithic IC. Single Data Rate (SDR) Pipelined (PL) read operations and Late Write (LW) write operations are supported,  
providing a high-performance user interface. Positive and negative output clocks are provided for applications requiring source-  
synchronous operation.  
All address and control input signals are registered on the rising edge of the CK differential input clock.  
During read operations, output data is driven valid once, from the rising edge of CK, one full cycle after the address and control  
signals are registered.  
During write operations, input data is registered once, on the rising edge of CK, one full cycle after the address and control  
signals are registered.  
Output drivers are series-terminated, and output impedance is programmable via the ZQ control pin. When an external resistor  
RQ is connected between ZQ and VSS, the impedance of the SRAM’s output drivers is set to ~RQ/5.  
300 MHz operation (300 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan interface is provided using  
a subset of IEEE standard 1149.1 protocol.  
Features  
3 Speed Bins  
Cycle Time / Data Access Time  
3.3ns / 1.8ns  
-33  
-4  
4.0ns / 2.1ns  
-5  
5.0ns / 2.3ns  
• Single 1.8V power supply (VDD): 1.7V (min) to 1.95V (max)  
• Dedicated output supply voltage (VDDQ): 1.4V (min) to VDD (max)  
• HSTL-compatible I/O interface with dedicated input reference voltage (VREF): VDDQ/2 typical  
• Common I/O  
• Single Data Rate (SDR) data transfers  
• Pipelined (PL) read operations  
• Late Write (LW) write operations  
• Burst capability with internally controlled Linear Burst address sequencing  
• Burst length of two, three, or four, with automatic address wrap  
• Full read/write data coherency  
• Byte write capability  
• Differential input clocks (CK and CK)  
• Data-referenced output clocks (CQ1, CQ1, CQ2, CQ2)  
• Programmable output driver impedance via dedicated control pin (ZQ)  
• Depth expansion capability (2 or 4 banks) via programmable chip enables (E2, E3, EP2, EP3)  
• JTAG boundary scan (subset of IEEE standard 1149.1)  
• 209 pin (11x19), 1mm pitch, 14mm x 22mm Ball Grid Array (BGA) package  
18Mb 1x1Lp, HSTL, rev 1.0  
1 / 30  
July 19, 2002  

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