Datasheet > CXK77P36L80GB

CXK77P36L80GB

更新时间： 2024-09-19 23:44:43

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
25页	221K
描述
MEMORY-UHS Synch SRAMs＜/A＞＜/I＞ 8Meg Ultra-High-Speed Synchronous SRAM (256K x 36) (25 pages 219K Rev. 11/03/02

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CXK77P36L80GB 数据手册

SONY

CXK77P36L80GB

4/42/43/44

8Mb LW R-L HSTL High Speed Synchronous SRAMs (256K x 36)

Preliminary

Description

The CXK77P36L80GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 262,144 words

by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output latches, and a one-deep write buffer

onto a single monolithic IC. Register - Latch (R-L) read operations and Late Write (LW) write operations are supported, pro-

viding a high-performance user interface.

All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of K

(Input Clock).

During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered.

During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.

The output drivers are series terminated, and the output impedance is programmable through an external impedance matching

resistor RQ. By connecting RQ between ZQ and V , the output impedance of all DQ pins can be precisely controlled.

Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single

3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.

Features

•

4 Speed Bins

-4 (-4A) (-4B)

Cycle Time / Access Time

4.0ns / 3.9ns (3.8ns) (3.7ns)

4.2ns / 4.2ns (4.1ns) (4.0ns)

4.3ns / 4.5ns (4.4ns) (4.3ns)

4.4ns / 4.7ns

-42 (-42A) (-42B)

-43 (-43A) (-43B)

-44

• Single 3.3V power supply (V ): 3.3V ± 5%

• Dedicated output supply voltage (V

): 1.9V typical

DDQ

• Extended HSTL-compatible I/O interface with dedicated input reference voltage (V

• Register - Latch (R-L) read operations

): 0.85V typical

REF

• Late Write (LW) write operations

• Full read/write coherency

• Byte Write capability

• One cycle deselect

• Differential input clocks (K/K)

• Asynchronous output enable (G)

• Programmable impedance output drivers

• Sleep (power down) mode via dedicated mode pin (ZZ)

• JTAG boundary scan (subset of IEEE standard 1149.1)

• 119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

8Mb LW R-L, rev 1.1

1 / 25

November 3, 2000

12 3 4 5 6 7...25

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与CXK77P36L80GB相关器件

型号	品牌	获取价格	描述	数据表
CXK77P36L80GB-42A	SONY	获取价格	Late-Write SRAM, 256KX36, 4.1ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77P36L80GB-43	SONY	获取价格	Late-Write SRAM, 256KX36, 4.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77P36L80GB-43A	SONY	获取价格	Late-Write SRAM, 256KX36, 4.4ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77P36L80GB-43B	SONY	获取价格	Late-Write SRAM, 256KX36, 4.3ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77P36L80GB-44	SONY	获取价格	Late-Write SRAM, 256KX36, 4.7ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77P36L80GB-4B	SONY	获取价格	Late-Write SRAM, 256KX36, 3.7ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77P36R160GB	ETC	获取价格	MEMORY-UHS Synch SRAMs＜/A＞＜I＞ 16Meg Ultra-Hig
CXK77P36R80GB	ETC	获取价格	MEMORY-UHS Synch SRAMS 8Meg Ultra-High-Speed Synchronous SRAM (256K x 36) (25 pages 246K R
CXK77P36R80GB-33	SONY	获取价格	Late-Write SRAM, 256KX36, 1.7ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77Q18162AGB-25	SONY	获取价格	DDR SRAM, 1MX18, 2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153

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