Datasheet > CXK77P36R160GB

CXK77P36R160GB

更新时间： 2024-11-07 23:44:43

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
22页	241K
描述
MEMORY-UHS Synch SRAMs＜/A＞＜I＞ 16Meg Ultra-High-Speed Synchronous SRAM (512K x 36) (22 pages 239K Rev. 6/24/02)

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CXK77P36R160GB 数据手册

SONYÒ CXK77P36R160GB / CXK77P18R160GB

3/33/4

16Mb LW R-R HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

Preliminary

Description

The CXK77P36R160GB (organized as 524,288 words by 36 bits) and the CXK77P18R160GB (organized as 1,048,576 words

by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input

registers, high speed RAM, output registers, and a one-deep write buffer onto a single monolithic IC. Register - Register (R-R)

read operations and Late Write (LW) write operations are supported, providing a high-performance user interface.

All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of the K

differential input clock.

During read operations, output data is driven valid from the rising edge of K, one full clock cycle after address is registered.

During write operations, input data is registered on the rising edge of K, one full clock cycle after address is registered.

Sleep (power down) capability is provided via the ZZ input signal.

Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external

control resistor RQ between ZQ and V , the impedance of all data output drivers can be precisely controlled.

333 MHz operation is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using a subset of

IEEE standard 1149.1 protocol.

Features

•

3 Speed Bins

Cycle Time / Access Time

3.0ns / 1.8ns

-3

-33

-4

3.3ns / 1.9ns

4.0ns / 2.0ns

•

Single 2.5V power supply (V ): 2.5V ± 5%

Dedicated output supply voltage (V

): 1.8V ± 0.1V

DDQ

HSTL-compatible I/O interface with dedicated input reference voltage (V ): 0.9V typical

REF

Late Write (LW) write protocol

Full read/write coherency

Byte Write capability

Differential input clocks (K/K)

Asynchronous output enable (G)

Sleep (power down) mode via dedicated mode pin (ZZ)

Programmable output driver impedance

JTAG boundary scan (subset of IEEE standard 1149.1)

119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

16Mb LW R-R, rev 1.0

1 / 22

June 24, 2002

12 3 4 5 6 7...22

中文翻译

下载PDF

与CXK77P36R160GB相关器件

型号	品牌	获取价格	描述	数据表
CXK77P36R80GB	ETC	获取价格	MEMORY-UHS Synch SRAMS 8Meg Ultra-High-Speed Synchronous SRAM (256K x 36) (25 pages 246K R
CXK77P36R80GB-33	SONY	获取价格	Late-Write SRAM, 256KX36, 1.7ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77Q18162AGB-25	SONY	获取价格	DDR SRAM, 1MX18, 2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q18162AGB-3	SONY	获取价格	DDR SRAM, 1MX18, 2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q18162AGB-3A	SONY	获取价格	DDR SRAM, 1MX18, 2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q18162GB-25	SONY	获取价格	DDR SRAM, 1MX18, 1.8ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q18162GB-27	SONY	获取价格	DDR SRAM, 1MX18, 1.9ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q18B80AGB	ETC	获取价格	MEMORY-UHS Synch SRAMs 8Meg Ultra-High-Speed Synchronous SRAM (512K x 18) (28 pages 315K R
CXK77Q18B80AGB-28	SONY	获取价格	Late-Write SRAM, 512KX18, 1.6ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77Q18B80AGB-4	SONY	获取价格	Late-Write SRAM, 512KX18, 2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119

与CXK77P36R160GB相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

21
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

20
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

44
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

38

产品中心

服务支持

精选活动

关于我们

帮助中心

CXK77P36R160GB

CXK77P36R160GB 数据手册

与CXK77P36R160GB相关器件

与CXK77P36R160GB相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CXK77P36R160GB

CXK77P36R160GB 数据手册

与CXK77P36R160GB相关器件

与CXK77P36R160GB相关文章

您还可以找

您在本页遇到什么问题？