Datasheet > CXK77Q36162GB

CXK77Q36162GB

更新时间： 2024-09-19 23:44:43

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
24页	312K
描述
MEMORY-UHS Synch SRAMs 16Meg Ultra-High-Speed Synchronous SRAM (512K x 36) (24 pages 311K Rev. 7/3/02)

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CXK77Q36162GB 数据手册

SONYÒ

CXK77Q36162GB

25/27/3

16Mb DDR1 HSTL High Speed Synchronous SRAM (512K x 36)

Preliminary

Description

The CXK77Q36162GB is a high speed CMOS synchronous static RAM with common I/O pins, organized as 524,288 words

by 36 bits. This synchronous SRAM integrates input registers, high speed RAM, output registers, and a two-deep write buffer

onto a single monolithic IC. Single Data Rate (SDR) and Double Data Rate (DDR) Register - Register (R-R) Read operations

and Late Write (LW) Write operations are supported, providing a flexible, high-performance user interface. Continue operations

are supported, providing burst capability. Positive and negative output clocks are provided for applications requiring source-

synchronous operation.

All address and control input signals except the G output enable signal are registered on the rising edge of the CK differential

input clock. All commands are input via the B(1:3) control signals.

During SDR read operations, output data is driven valid once, from the rising edge of CK, one full clock cycle after the address

is registered. During DDR read operations, output data is driven valid twice, first from the rising edge of CK and then from the

falling edge of CK, beginning one full clock cycle after the address is registered. In both cases, output data transitions are closely

aligned with output clock transitions.

During SDR write operations, input data is registered once, on the rising edge of CK, one full clock cycle after the address is

registered. During DDR write operations, input data is registered twice, first on the rising edge of CK and then on the falling

edge of CK, beginning one full clock cycle after the address is registered.

Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external

control resistor RQ between ZQ and V , the impedance of all data and clock output drivers can be precisely controlled.

400 MHz operation (800 Mbps) is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using

a subset of IEEE standard 1149.1 protocol.

Features

•

3 Speed Bins

Cycle Time / Access Time

2.5ns / 1.8ns

Data Rate

800 Mbps

740 Mbps

666 Mbps

-25

-27

-3

2.7ns / 1.9ns

3.0ns / 2.0ns

•

Single 2.5V power supply (V ): 2.5V ± 5%

Dedicated output supply voltage (V

): 1.5V ± 0.1V

DDQ

HSTL-compatible I/O interface with dedicated input reference voltage (V ): 0.75V typical

REF

DDR1 functional compatibility

Late Write (LW) write protocol

Single Data Rate (SDR) and Double Data Rate (DDR) data transfers

Burst capability via Continue commands

Linear or interleaved burst order, selectable via dedicated mode pin (LBO)

Full read/write coherency

Two cycle deselect

Differential input clocks (CK/CK)

Positive and negative output clocks (CQ/CQ) - one pair per 18 bits of output data (DQ)

Asynchronous output enable (G)

Programmable output driver impedance

JTAG boundary scan (subset of IEEE standard 1149.1)

153 pin (9x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

16Mb DDR1, rev 1.0

1 / 24

July 3, 2002

12 3 4 5 6 7...24

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与CXK77Q36162GB相关器件

型号	品牌	获取价格	描述	数据表
CXK77Q36162GB-25	SONY	获取价格	DDR SRAM, 512KX36, 1.8ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q36162GB-27	SONY	获取价格	DDR SRAM, 512KX36, 1.9ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q36162GB-3	SONY	获取价格	DDR SRAM, 512KX36, 2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q36B160GB	ETC	获取价格	MEMORY-UHS Synch SRAMs 16Meg Ultra-High-Speed Synchronous SRAM (512K x 36) (25 pages 295K
CXK77Q36B160GB-28	SONY	获取价格	Late-Write SRAM, 512KX36, 1.5ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77Q36B160GB-4	SONY	获取价格	Late-Write SRAM, 512KX36, 1.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77Q36B160GB-4A	SONY	获取价格	Standard SRAM, 512KX36, 1.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77Q36B80AGB	ETC	获取价格	MEMORY-UHS Synch SRAMs 8Meg Ultra-High-Speed Synchronous SRAM (256K x 36) (28 pages 315K R
CXK77Q36B80AGB-28	SONY	获取价格	Late-Write SRAM, 256KX36, 1.6ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77Q36B80AGB-33	SONY	获取价格	Late-Write SRAM, 256KX36, 1.6ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11

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