Datasheet > CXK77Q36R160GB

CXK77Q36R160GB

更新时间： 2024-11-28 23:44:43

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
23页	162K
描述
MEMORY-UHS Synch SRAMs 16Meg Ultra-High-Speed Synchronous SRAM (512K x 36) (23 pages 162K Rev. 8/20/01＞

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中文翻译

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数据手册

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CXK77Q36R160GB 数据手册

SONYÒ CXK77Q36R160GB / CXK77Q18R160GB

3/33/4

16Mb LW R-R HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

Preliminary

Description

The CXK77Q36R160GB (organized as 524,288 words by 36 bits) and the CXK77Q18R160GB (organized as 1,048,576 words

by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input

registers, high speed RAM, output registers, and a one-deep write buffer onto a single monolithic IC. Register - Register (R-R)

read operations and Late Write (LW) write operations are supported, providing a high-performance user interface.

All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of K

(Input Clock).

During read operations, output data is driven valid from the rising edge of K, one full clock cycle after the address is registered.

During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.

The output drivers are series terminated, and the output impedance is programmable through an external impedance matching

resistor RQ. By connecting RQ between ZQ and V , the output impedance of all DQ pins can be precisely controlled.

Sleep (power down) mode control is provided through the asynchronous ZZ input. 333 MHz operation is obtained from a single

2.5V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.

Features

•

3 Speed Bins

Cycle Time / Access Time

3.0ns / 1.8ns

-3

-33

-4

3.3ns / 1.9ns

4.0ns / 2.0ns

•

Single 2.5V power supply (V ): 2.5V ± 5%

Dedicated output supply voltage (V

): 1.5V typical

DDQ

HSTL-compatible I/O interface with dedicated input reference voltage (V ): 0.75V typical

REF

Late Write (LW)

Full read/write coherency

Byte Write capability

Two cycle deselect

Differential input clocks (K/K)

Asynchronous output enable (G)

Programmable impedance output drivers

Sleep (power down) mode via dedicated mode pin (ZZ)

JTAG boundary scan (subset of IEEE standard 1149.1)

119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

16Mb LW R-R, rev 0.1

1 / 23

August 20, 2001

12 3 4 5 6 7...23

中文翻译

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与CXK77Q36R160GB相关器件

型号	品牌	获取价格	描述	数据表
CXK77Q36R160GB-3	SONY	获取价格	Standard SRAM, 512KX36, 1.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77Q36R160GB-33	SONY	获取价格	Standard SRAM, 512KX36, 1.9ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77Q36R160GB-4	SONY	获取价格	Standard SRAM, 512KX36, 2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77R1882AGB-35	SONY	获取价格	DDR SRAM, 512KX18, 2.2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77R1882AGB-39	SONY	获取价格	DDR SRAM, 512KX18, 2.6ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77R1882AGB-39A	SONY	获取价格	DDR SRAM, 512KX18, 2.4ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77R1882AGB-42	SONY	获取价格	DDR SRAM, 512KX18, 2.6ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77R3682AGB-35	SONY	获取价格	DDR SRAM, 256KX36, 2.2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77R3682AGB-39	SONY	获取价格	DDR SRAM, 256KX36, 2.6ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77R3682AGB-39A	SONY	获取价格	DDR SRAM, 256KX36, 2.4ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153

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