Datasheet > CXK77R1882AGB-35

CXK77R1882AGB-35

更新时间： 2024-11-29 21:01:55

品牌	Logo	应用领域
索尼 - SONY		时钟双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
28页	277K
描述
DDR SRAM, 512KX18, 2.2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153

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中文翻译

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技术参数
数据手册

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CXK77R1882AGB-35 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA, BGA153,9X17,50	针数：	153
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	2.2 ns	最大时钟频率 (fCLK)：	285 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B153
JESD-609代码：	e0	长度：	22 mm
内存密度：	9437184 bit	内存集成电路类型：	DDR SRAM
内存宽度：	18	功能数量：	1
端子数量：	153	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：
组织：	512KX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA153,9X17,50	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240	电源：	1.5/1.8,2.5 V
认证状态：	Not Qualified	座面最大高度：	2.3 mm
最大待机电流：	0.44 A	最小待机电流：	2.38 V
子类别：	SRAMs	最大压摆率：	0.88 mA
最大供电电压 (Vsup)：	2.63 V	最小供电电压 (Vsup)：	2.37 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	10	宽度：	14 mm
Base Number Matches：	1

CXK77R1882AGB-35 数据手册

SONY

CXK77R3682AGB / CXK77R1882AGB

35/39/42

8Mb Double Data Rate HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18 Organization)

Preliminary

Description

The CXK77R3682AGB (organized as 262,144 words by 36 bits) and the CXK77R1882AGB (organized as 524,288 words by

18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input

registers, high speed RAM, output registers, and a two-deep write buffer onto a single monolithic IC. Burst and non-burst single

data rate (SDR) and double data rate (DDR) Register - Register (R-R) read operations and Late Write (LW) write operations are

supported, providing a flexible, high-performance user interface.

All address and control input signals except G (Output Enable) are registered on the rising edge of CK (Input Clock). Burst and

non-burst, SDR and DDR read and write operations are initiated, on a cycle-by-cycle basis, via external control pins B(1:3).

During SDR read operations, output data is driven valid once, from the rising edge of CK, one full clock cycle after the address

is registered. During DDR read operations, output data is driven valid twice, first from the rising edge of CK and then from the

falling edge of CK, beginning one full clock cycle after the address is registered. One pair of output clocks (CQ/CQ) is provided

with each 18-bit word of output data. The timing relationship between each pair of output clocks and its corresponding word of

output data is precisely controlled.

During SDR write operations, input data is registered once, on the rising edge of CK, one full clock cycle after the address is

registered. During DDR write operations, input data is registered twice, first on the rising edge of CK and then on the falling

edge of CK, beginning one full clock cycle after the address is registered.

The output drivers are series terminated, and the output impedance is programmable through an external impedance matching

resistor RQ. By connecting RQ between ZQ and V , the output impedance of all DQ and CQ pins can be precisely controlled.

285 MHz operation (570 Mbps) is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using

a subset of IEEE standard 1149.1 protocol.

Features

•

3 Speed Bins

-35

Cycle Time / Access Time

3.5ns / 2.2ns

Data Rate

570 Mbps

512 Mbps

476 Mbps

-39 (-39A)

-42

3.9ns / 2.6ns (2.4ns)

4.2ns / 2.6ns

• Single 2.5V power supply (V ): 2.5V ± 5%

• Register - Register (R-R) read operations

• Late Write (LW), fully coherent write operations

• Single and double data rate burst read and write operations

• Linear or interleaved burst order, selectable via dedicated mode pin (LBO)

• Burst length of two, three, or four, with automatic address wrap

• Two cycle deselect

• One pair of differential input clocks (CK/CK)

• One pair of output clocks (CQ/CQ) per 18 bits of output data (DQ)

• Asynchronous output enable (G)

• Dedicated output supply voltage (V

): 1.5V to 1.8V typical

DDQ

• HSTL-compatible I/O interface with dedicated input reference voltage (V ): V

/2 typical

DDQ

REF

• Programmable impedance output drivers

• Stop-Clock capability

• JTAG boundary scan (subset of IEEE standard 1149.1)

• 153 pin (9x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

8Mb, Sync DDR, HSTL, rev 1.2

1 / 28

August 25, 2000

12 3 4 5 6 7...28

中文翻译

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与CXK77R1882AGB-35相关器件

型号	品牌	获取价格	描述	数据表
CXK77R1882AGB-39	SONY	获取价格	DDR SRAM, 512KX18, 2.6ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77R1882AGB-39A	SONY	获取价格	DDR SRAM, 512KX18, 2.4ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77R1882AGB-42	SONY	获取价格	DDR SRAM, 512KX18, 2.6ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77R3682AGB-35	SONY	获取价格	DDR SRAM, 256KX36, 2.2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77R3682AGB-39	SONY	获取价格	DDR SRAM, 256KX36, 2.6ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77R3682AGB-39A	SONY	获取价格	DDR SRAM, 256KX36, 2.4ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77R3682AGB-42	SONY	获取价格	DDR SRAM, 256KX36, 2.6ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77S18L80AGB-4	SONY	获取价格	Late-Write SRAM, 512KX18, 3.9ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77S18L80AGB-42	SONY	获取价格	Late-Write SRAM, 512KX18, 4.2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77S18L80AGB-42A	SONY	获取价格	Late-Write SRAM, 512KX18, 4.1ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119

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