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CXK77S18L80AGB-42A PDF预览

CXK77S18L80AGB-42A

更新时间: 2024-11-29 18:02:19
品牌 Logo 应用领域
索尼 - SONY 静态存储器内存集成电路
页数 文件大小 规格书
24页 254K
描述
Late-Write SRAM, 512KX18, 4.1ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119

CXK77S18L80AGB-42A 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:BGA, BGA119,7X17,50针数:119
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.92
Is Samacsys:N最长访问时间:4.1 ns
I/O 类型:COMMONJESD-30 代码:R-PBGA-B119
JESD-609代码:e0长度:22 mm
内存密度:9437184 bit内存集成电路类型:LATE-WRITE SRAM
内存宽度:18功能数量:1
端子数量:119字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:512KX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):240电源:1.9,3.3 V
认证状态:Not Qualified座面最大高度:2.5 mm
最大待机电流:0.1 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.75 mA
最大供电电压 (Vsup):3.47 V最小供电电压 (Vsup):3.13 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:10宽度:14 mm
Base Number Matches:1

CXK77S18L80AGB-42A 数据手册

 浏览型号CXK77S18L80AGB-42A的Datasheet PDF文件第2页浏览型号CXK77S18L80AGB-42A的Datasheet PDF文件第3页浏览型号CXK77S18L80AGB-42A的Datasheet PDF文件第4页浏览型号CXK77S18L80AGB-42A的Datasheet PDF文件第5页浏览型号CXK77S18L80AGB-42A的Datasheet PDF文件第6页浏览型号CXK77S18L80AGB-42A的Datasheet PDF文件第7页 
SONY  
CXK77S36L80AGB / CXK77S18L80AGB 4/42/43/44  
8Mb Late Write HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18 Organization)  
Preliminary  
Description  
The CXK77S36L80AGB (organized as 262,144 words by 36 bits) and the CXK77S18L80AGB (organized as 524,288 words  
by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input  
registers, high speed RAM, output latches, and a one-deep write buffer onto a single monolithic IC. Register - Latch (R-L) read  
operations and Late Write (LW) write operations are supported, providing a high-performance user interface.  
All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of K  
(Input Clock).  
During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered.  
During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered. Write  
operations are internally self-timed, eliminating the need for complex off-chip write pulse generation.  
The output drivers are series terminated, and the output impedance is programmable through an external impedance matching  
resistor RQ. By connecting RQ between ZQ and VSS, the output impedance of all DQ pins can be precisely controlled.  
Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single  
3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.  
Features  
4 Speed Bins  
-4 (-4A) (-4B)  
Cycle Time / Access Time  
4.0ns / 3.9ns (3.8ns) (3.7ns)  
4.2ns / 4.2ns (4.1ns) (4.0ns)  
4.3ns / 4.5ns (4.4ns) (4.3ns)  
4.4ns / 4.7ns  
-42 (-42A) (-42B)  
-43 (-43A) (-43B)  
-44  
• Single 3.3V power supply (VDD): 3.3V ± 5%  
• Register - Latch (R-L) read operations  
• Late Write (LW), fully coherent, self-timed write operations  
• Byte Write capability  
• One cycle deselect  
• Differential input clocks (K/K)  
• Asynchronous output enable (G)  
• Dedicated output supply voltage (VDDQ): 1.9V typical  
• Extended HSTL-compatible I/O interface with dedicated input reference voltage (VREF): 0.85V typical  
• Programmable impedance output drivers  
• Sleep (power down) mode via dedicated mode pin (ZZ)  
• JTAG boundary scan (subset of IEEE standard 1149.1)  
• 119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package  
8Mb, Sync LW, R-L, HSTL, rev 1.3  
1 / 24  
June 23, 2000  

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CXK77S18R80AGB-4 SONY

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Late-Write SRAM, 512KX18, 2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77S18R80AGB-4A SONY

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Late-Write SRAM, 512KX18, 1.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77S36L80AGB-4 SONY

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Late-Write SRAM, 256KX36, 3.9ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77S36L80AGB-42 SONY

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Late-Write SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119