Datasheet > CXK77Q36B80AGB

CXK77Q36B80AGB

更新时间： 2024-09-19 23:44:43

品牌	Logo	应用领域
其他 - ETC		静态存储器
页数	文件大小	规格书
28页	317K
描述
MEMORY-UHS Synch SRAMs 8Meg Ultra-High-Speed Synchronous SRAM (256K x 36) (28 pages 315K Rev. 10/18/01)

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中文翻译

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数据手册

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CXK77Q36B80AGB 数据手册

SONYÒ CXK77Q36B80AGB / CXK77Q18B80AGB 28/33/37/4

8Mb LW LS R-R HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18)

Preliminary

Description

The CXK77Q36B80AGB (organized as 262,144 words by 36 bits) and the CXK77Q18B80AGB (organized as 524,288 words

by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input

registers, high speed RAM, output registers, and a one-deep write buffer onto a single monolithic IC. Register - Register (R-R)

read operations and Late Write (LW) write operations are supported, providing a high-performance user interface.

Two distinct R-R modes of operation are supported, selectable via the M2 mode pin. When M2 is “high”, these devices function

as conventional R-R SRAMs, and pin 4P functions as a conventional SA address input. When M2 is “low”, these devices func-

tion as Late Select (LS) R-R SRAMs, and pin 4P functions as a Late Select SAS address input.

When Late Select R-R mode is selected, the SRAM is divided into two banks internally. During write operations, SAS is reg-

istered in the same cycle as the other address and control signals, and is used to select to which bank input data is ultimately

written (through one stage of write pipelining). During read operations, SAS is registered one full clock cycle after the other

address and control signals, and is used to select from which bank output data is read.

All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of K

(Input Clock).

During read operations, output data is driven valid from the rising edge of K, one full clock cycle after all address and control

input signals (except SAS) are registered.

During write operations, input data is registered on the rising edge of K, one full clock cycle after all address and control input

signals (including SAS) are registered.

The output drivers are series terminated, and the output impedance is programmable through an external impedance matching

resistor RQ. By connecting RQ between ZQ and V , the output impedance of all DQ pins can be precisely controlled.

Sleep (power down) mode control is provided through the asynchronous ZZ input. 350 MHz operation is obtained from a single

2.5V or 3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.

Features

•

4 Speed Bins

-28

Cycle Time / Access Time

2.8ns / 1.6ns

-33

3.3ns / 1.6ns

-37 (-37A)

-4 (-4A)

3.7ns / 1.8ns (1.6ns)

4.0ns / 2.0ns (1.8ns)

•

Single 2.5V or 3.3V power supply (V ): 2.5V ± 5% or 3.3V ± 5%

Dedicated output supply voltage (V

): 1.5V or 1.8V typical

DDQ

HSTL-compatible I/O interface with dedicated input reference voltage (V ):V

/2 typical

DDQ

REF

Late Write (LW) write operations

Conventional or Late Select (LS) mode of operation, selectable via dedicated mode pin (M2)

Full read/write coherency

Byte Write capability

Two cycle deselect

Differential input clocks (K/K)

Asynchronous output enable (G)

Programmable impedance output drivers

Sleep (power down) mode via dedicated mode pin (ZZ)

JTAG boundary scan (subset of IEEE standard 1149.1)

119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

8Mb LW R-R and R-R w/ LS, rev 1.6

1 / 28

October 18, 2001

12 3 4 5 6 7...28

中文翻译

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与CXK77Q36B80AGB相关器件

型号	品牌	获取价格	描述	数据表
CXK77Q36B80AGB-28	SONY	获取价格	Late-Write SRAM, 256KX36, 1.6ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77Q36B80AGB-33	SONY	获取价格	Late-Write SRAM, 256KX36, 1.6ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77Q36B80AGB-37A	SONY	获取价格	Late-Write SRAM, 256KX36, 1.6ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77Q36B80AGB-4	SONY	获取价格	Late-Write SRAM, 256KX36, 2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
CXK77Q36B80AGB-4A	SONY	获取价格	Late-Write SRAM, 256KX36, 1.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77Q36R160GB	ETC	获取价格	MEMORY-UHS Synch SRAMs 16Meg Ultra-High-Speed
CXK77Q36R160GB-3	SONY	获取价格	Standard SRAM, 512KX36, 1.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77Q36R160GB-33	SONY	获取价格	Standard SRAM, 512KX36, 1.9ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77Q36R160GB-4	SONY	获取价格	Standard SRAM, 512KX36, 2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77R1882AGB-35	SONY	获取价格	DDR SRAM, 512KX18, 2.2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153

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