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CXK77Q18B80AGB-4 PDF预览

CXK77Q18B80AGB-4

更新时间： 2024-11-08 20:52:39
品牌 Logo 应用领域
索尼 - SONY 时钟静态存储器内存集成电路
页数 文件大小 规格书
28页 314K
描述
Late-Write SRAM, 512KX18, 2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119

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CXK77Q18B80AGB-4 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA, BGA119,7X17,50针数：119
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.92
最长访问时间：2 ns最大时钟频率 (fCLK)：250 MHz
I/O 类型：COMMONJESD-30 代码：R-PBGA-B119
JESD-609代码：e0长度：22 mm
内存密度：9437184 bit内存集成电路类型：LATE-WRITE SRAM
内存宽度：18功能数量：1
端子数量：119字数：524288 words
字数代码：512000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：
组织：512KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA119,7X17,50封装形状：RECTANGULAR
封装形式：GRID ARRAY并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：1.5/1.8,2.5/3.3 V
认证状态：Not Qualified座面最大高度：2.4 mm
最大待机电流：0.1 A最小待机电流：2.38 V
子类别：SRAMs最大压摆率：0.6 mA
最大供电电压 (Vsup)：3.47 V最小供电电压 (Vsup)：2.37 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：OTHER
端子面层：TIN LEAD端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：10宽度：14 mm
Base Number Matches：1

CXK77Q18B80AGB-4 数据手册

 浏览型号CXK77Q18B80AGB-4的Datasheet PDF文件第2页浏览型号CXK77Q18B80AGB-4的Datasheet PDF文件第3页浏览型号CXK77Q18B80AGB-4的Datasheet PDF文件第4页浏览型号CXK77Q18B80AGB-4的Datasheet PDF文件第5页浏览型号CXK77Q18B80AGB-4的Datasheet PDF文件第6页浏览型号CXK77Q18B80AGB-4的Datasheet PDF文件第7页 
SONYÒ CXK77Q36B80AGB / CXK77Q18B80AGB 28/33/37/4  
8Mb LW LS R-R HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18)  
Preliminary  
Description  
The CXK77Q36B80AGB (organized as 262,144 words by 36 bits) and the CXK77Q18B80AGB (organized as 524,288 words  
by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input  
registers, high speed RAM, output registers, and a one-deep write buffer onto a single monolithic IC. Register - Register (R-R)  
read operations and Late Write (LW) write operations are supported, providing a high-performance user interface.  
Two distinct R-R modes of operation are supported, selectable via the M2 mode pin. When M2 is “high”, these devices function  
as conventional R-R SRAMs, and pin 4P functions as a conventional SA address input. When M2 is “low”, these devices func-  
tion as Late Select (LS) R-R SRAMs, and pin 4P functions as a Late Select SAS address input.  
When Late Select R-R mode is selected, the SRAM is divided into two banks internally. During write operations, SAS is reg-  
istered in the same cycle as the other address and control signals, and is used to select to which bank input data is ultimately  
written (through one stage of write pipelining). During read operations, SAS is registered one full clock cycle after the other  
address and control signals, and is used to select from which bank output data is read.  
All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of K  
(Input Clock).  
During read operations, output data is driven valid from the rising edge of K, one full clock cycle after all address and control  
input signals (except SAS) are registered.  
During write operations, input data is registered on the rising edge of K, one full clock cycle after all address and control input  
signals (including SAS) are registered.  
The output drivers are series terminated, and the output impedance is programmable through an external impedance matching  
resistor RQ. By connecting RQ between ZQ and V , the output impedance of all DQ pins can be precisely controlled.  
SS  
Sleep (power down) mode control is provided through the asynchronous ZZ input. 350 MHz operation is obtained from a single  
2.5V or 3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.  
Features  
•
4 Speed Bins  
-28  
Cycle Time / Access Time  
2.8ns / 1.6ns  
-33  
3.3ns / 1.6ns  
-37 (-37A)  
-4 (-4A)  
3.7ns / 1.8ns (1.6ns)  
4.0ns / 2.0ns (1.8ns)  
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single 2.5V or 3.3V power supply (V ): 2.5V ± 5% or 3.3V ± 5%  
DD  
Dedicated output supply voltage (V  
): 1.5V or 1.8V typical  
DDQ  
HSTL-compatible I/O interface with dedicated input reference voltage (V ):V  
/2 typical  
DDQ  
REF  
Register - Register (R-R) read operations  
Late Write (LW) write operations  
Conventional or Late Select (LS) mode of operation, selectable via dedicated mode pin (M2)  
Full read/write coherency  
Byte Write capability  
Two cycle deselect  
Differential input clocks (K/K)  
Asynchronous output enable (G)  
Programmable impedance output drivers  
Sleep (power down) mode via dedicated mode pin (ZZ)  
JTAG boundary scan (subset of IEEE standard 1149.1)  
119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package  
8Mb LW R-R and R-R w/ LS, rev 1.6  
1 / 28  
October 18, 2001  
1234567...28

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与CXK77Q18B80AGB-4相关器件

型号 品牌 获取价格 描述 数据表
CXK77Q18B80AGB-4A SONY

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 		Late-Write SRAM, 512KX18, 1.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77Q18R160GB ETC

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 		MEMORY-UHS Synch SRAMS 16Meg Ultra-High-Speed Synchronous SRAM (1M x 18) (23 pages 161K Re
CXK77Q18R160GB-3 SONY

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 		Standard SRAM, 1MX18, 1.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77Q18R160GB-4 SONY

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 		Standard SRAM, 1MX18, 2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119
CXK77Q36162AGB-3A SONY

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 		DDR SRAM, 512KX36, 2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q36162GB ETC

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 		MEMORY-UHS Synch SRAMs 16Meg Ultra-High-Speed Synchronous SRAM (512K x 36) (24 pages 311K
CXK77Q36162GB-25 SONY

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 		DDR SRAM, 512KX36, 1.8ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q36162GB-27 SONY

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 		DDR SRAM, 512KX36, 1.9ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q36162GB-3 SONY

获取价格

 		DDR SRAM, 512KX36, 2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q36B160GB ETC

获取价格

 		MEMORY-UHS Synch SRAMs 16Meg Ultra-High-Speed Synchronous SRAM (512K x 36) (25 pages 295K

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