Datasheet > CXK77Q18162AGB-25

CXK77Q18162AGB-25

更新时间： 2024-09-20 14:41:35

品牌	Logo	应用领域
索尼 - SONY		时钟双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
25页	319K
描述
DDR SRAM, 1MX18, 2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153

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技术参数
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CXK77Q18162AGB-25 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA, BGA153,9X17,50	针数：	153
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
Is Samacsys：	N	最长访问时间：	2 ns
其他特性：	LATE WRITE	最大时钟频率 (fCLK)：	400 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B153
JESD-609代码：	e0	长度：	22 mm
内存密度：	18874368 bit	内存集成电路类型：	DDR SRAM
内存宽度：	18	功能数量：	1
端子数量：	153	字数：	1048576 words
字数代码：	1000000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：
组织：	1MX18	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA153,9X17,50	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	240	电源：	1.5,2.5 V
认证状态：	Not Qualified	座面最大高度：	2.5 mm
最大待机电流：	0.25 A	最小待机电流：	2.37 V
子类别：	SRAMs	最大压摆率：	0.89 mA
最大供电电压 (Vsup)：	2.63 V	最小供电电压 (Vsup)：	2.37 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	10	宽度：	14 mm
Base Number Matches：	1

CXK77Q18162AGB-25 数据手册

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SONYÒ CXK77Q36162AGB / CXK77Q18162AGB

25/27/3

16Mb DDR1 HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)

Preliminary

Description

The CXK77Q36162AGB (organized as 524,288 words by 36 bits) and the CXK77Q18162AGB (organized as 1,048,576 words

by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input

registers, high speed RAM, output registers, and a two-deep write buffer onto a single monolithic IC. Single Data Rate (SDR)

and Double Data Rate (DDR) Register - Register (R-R) Read operations and Late Write (LW) Write operations are supported,

providing a flexible, high-performance user interface. Continue operations are supported, providing burst capability. Positive

and negative output clocks are provided for applications requiring source-synchronous operation.

All address and control input signals except the G output enable signal are registered on the rising edge of the CK differential

input clock. All commands are input via the B(1:3) control signals.

During SDR read operations, output data is driven valid once, from the rising edge of CK, one full clock cycle after the address

is registered. During DDR read operations, output data is driven valid twice, first from the rising edge of CK and then from the

falling edge of CK, beginning one full clock cycle after the address is registered. In both cases, output data transitions are closely

aligned with output clock transitions.

During SDR write operations, input data is registered once, on the rising edge of CK, one full clock cycle after the address is

registered. During DDR write operations, input data is registered twice, first on the rising edge of CK and then on the falling

edge of CK, beginning one full clock cycle after the address is registered.

Output drivers are series terminated, and output impedance is programmable via the ZQ input pin. By connecting an external

control resistor RQ between ZQ and V , the impedance of all data and clock output drivers can be precisely controlled.

400 MHz operation (800 Mbps) is obtained from a single 2.5V power supply. JTAG boundary scan interface is provided using

a subset of IEEE standard 1149.1 protocol.

Features

•

3 Speed Bins

-25 (-25A)

Cycle Time / Access Time

2.5ns / 2.0ns (1.8ns)

2.7ns / 2.1ns (1.9ns)

3.0ns / 2.2ns (2.0ns)

Data Rate

800 Mbps

740 Mbps

666 Mbps

-27 (-27A)

-3 (-3A)

•

Single 2.5V power supply (V ): 2.5V ± 5%

Dedicated output supply voltage (V

): 1.5V to 1.6V typical

DDQ

HSTL-compatible I/O interface with dedicated input reference voltage (V ): V

/2 typical

DDQ

REF

DDR1 functional compatibility

Late Write (LW) write protocol

Single Data Rate (SDR) and Double Data Rate (DDR) data transfers

Burst capability via Continue commands

Linear or interleaved burst order, selectable via dedicated mode pin (LBO)

Full read/write coherency

Two cycle deselect

Differential input clocks (CK/CK)

Positive and negative output clocks (CQ/CQ) - one pair per 18 bits of output data (DQ)

Asynchronous output enable (G)

Programmable output driver impedance

JTAG boundary scan (subset of IEEE standard 1149.1)

153 pin (9x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package

16Mb DDR1, rev 0.1

1 / 25

November 16, 2001

12 3 4 5 6 7...25

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与CXK77Q18162AGB-25相关器件

型号	品牌	获取价格	描述	数据表
CXK77Q18162AGB-3	SONY	获取价格	DDR SRAM, 1MX18, 2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q18162AGB-3A	SONY	获取价格	DDR SRAM, 1MX18, 2ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q18162GB-25	SONY	获取价格	DDR SRAM, 1MX18, 1.8ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q18162GB-27	SONY	获取价格	DDR SRAM, 1MX18, 1.9ns, CMOS, PBGA153, 14 X 22 MM, 1.27 MM PITCH, BGA-153
CXK77Q18B80AGB	ETC	获取价格	MEMORY-UHS Synch SRAMs 8Meg Ultra-High-Speed Synchronous SRAM (512K x 18) (28 pages 315K R
CXK77Q18B80AGB-28	SONY	获取价格	Late-Write SRAM, 512KX18, 1.6ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77Q18B80AGB-4	SONY	获取价格	Late-Write SRAM, 512KX18, 2ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119
CXK77Q18B80AGB-4A	SONY	获取价格	Late-Write SRAM, 512KX18, 1.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-11
CXK77Q18R160GB	ETC	获取价格	MEMORY-UHS Synch SRAMS 16Meg Ultra-High-Speed Synchronous SRAM (1M x 18) (23 pages 161K Re
CXK77Q18R160GB-3	SONY	获取价格	Standard SRAM, 1MX18, 1.8ns, CMOS, PBGA119, 14 X 22 MM, 1.27 MM PITCH, BGA-119

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